skip to main content


Title: Few‐Layer GeAs Field‐Effect Transistors and Infrared Photodetectors
Abstract

The family of 2D semiconductors (2DSCs) has grown rapidly since the first isolation of graphene. The emergence of each 2DSC material brings considerable excitement for its unique electrical, optical, and mechanical properties, which are often highly distinct from their 3D counterparts. To date, studies of 2DSC are majorly focused on group IV (e.g., graphene, silicene), group V (e.g., phosphorene), or group VIB compounds (transition metal dichalcogenides, TMD), and have inspired considerable effort in searching for novel 2DSCs. Here, the first electrical characterization of group IV–V compounds is presented by investigating few‐layer GeAs field‐effect transistors. With back‐gate device geometry, p‐type behaviors are observed at room temperature. Importantly, the hole carrier mobility is found to approach 100 cm2V−1s−1with ON–OFF ratio over 105, comparable well with state‐of‐the‐art TMD devices. With the unique crystal structure the few‐layer GeAs show highly anisotropic optical and electronic properties (anisotropic mobility ratio of 4.8). Furthermore, GeAs based transistor shows prominent and rapid photoresponse to 1.6 µm radiation with a photoresponsivity of 6 A W−1and a rise and fall time of ≈3 ms. This study of group IV–V 2DSC materials greatly expands the 2D family, and can enable new opportunities in functional electronics and optoelectronics based on 2DSCs.

 
more » « less
NSF-PAR ID:
10055758
Author(s) / Creator(s):
 ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  ;  
Publisher / Repository:
Wiley Blackwell (John Wiley & Sons)
Date Published:
Journal Name:
Advanced Materials
Volume:
30
Issue:
21
ISSN:
0935-9648
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. Abstract

    Semiconductive transition metal dichalcogenides (TMDs) have been considered as next generation semiconductors, but to date most device investigations are still based on microscale exfoliation with a low yield. Wafer scale growth of TMDs has been reported but effective doping approaches remain challenging due to their atomically thick nature. This work reports the synthesis of wafer‐scale continuous few‐layer PtSe2films with effective doping in a controllable manner. Chemical component analyses confirm that both n‐doping and p‐doping can be effectively modulated through a controlled selenization process. The electrical properties of PtSe2films have been systematically studied by fabricating top‐gated field effect transistors (FETs). The device current on/off ratio is optimized in two‐layer PtSe2FETs, and four‐terminal configuration displays a reasonably high effective field effect mobility (14 and 15 cm2V−1s−1for p‐type and n‐type FETs, respectively) with a nearly symmetric p‐type and n‐type performance. Temperature dependent measurement reveals that the variable range hopping is dominant at low temperatures. To further establish feasible application based on controllable doping of PtSe2, a logic inverter and vertically stacked p–n junction arrays are demonstrated. These results validate that PtSe2is a promising candidate among the family of TMDs for future functional electronic applications.

     
    more » « less
  2. null (Ed.)
    Two-dimensional (2D) transition metal dichalcogenide (TMD) layers have gained increasing attention for a variety of emerging electrical, thermal, and optical applications. Recently developed metallic 2D TMD layers have been projected to exhibit unique attributes unattainable in their semiconducting counterparts; e.g. , much higher electrical and thermal conductivities coupled with mechanical flexibility. In this work, we explored 2D platinum ditelluride (2D PtTe 2 ) layers – a relatively new class of metallic 2D TMDs – by studying their previously unexplored electro-thermal properties for unconventional window applications. We prepared wafer-scale 2D PtTe 2 layer-coated optically transparent and mechanically flexible willow glasses via a thermally-assisted tellurization of Pt films at a low temperature of 400 °C. The 2D PtTe 2 layer-coated windows exhibited a thickness-dependent optical transparency and electrical conductivity of >10 6 S m −1 – higher than most of the previously explored 2D TMDs. Upon the application of electrical bias, these windows displayed a significant increase in temperature driven by Joule heating as confirmed by the infrared (IR) imaging characterization. Such superior electro-thermal conversion efficiencies inherent to 2D PtTe 2 layers were utilized to demonstrate various applications, including thermochromic displays and electrically-driven defogging windows accompanying mechanical flexibility. Comparisons of these performances confirm the superiority of the wafer-scale 2D PtTe 2 layers over other nanomaterials explored for such applications. 
    more » « less
  3. Abstract

    2D carbides and nitrides (MXenes) are widely recognized for their exceptional promise for numerous applications. However, physical property measurements of their individual monolayers remain very limited despite their importance for revealing the intrinsic physical properties of MXenes. The first mechanical and electrical measurements of individual single‐layer flakes of Nb4C3TxMXene, which are prepared via an improved synthetic method are reported. Characterization of field‐effect transistor devices based on individual single‐layer Nb4C3Txflakes shows an electrical conductivity of 1024 ± 165 S cm−1, which is two orders of magnitude higher than the previously reported values for bulk Nb4C3Txassemblies, and an electron mobility of 0.41 ± 0.27 cm2V−1s−1. Atomic force microscopy nanoindentation measurements of monolayer Nb4C3Txmembranes yield an effective Young's modulus of 386 ± 13 GPa, assuming a membrane thickness of 1.26 nm. This is the highest value reported for nanoindentation measurements of solution‐processable 2D materials, revealing the potential of Nb4C3Txas a primary component for various mechanical applications. Finally, the agreement between the mechanical properties of 2D Nb4C3TxMXene and cubic NbC suggests that the extensive experimental data on bulk carbides could be useful for identifying new MXenes with improved functional characteristics.

     
    more » « less
  4. In recent years, oxide electronics has emerged as one of the most promising new technologies for a variety of electrical and optoelectronic applications, including next-generation displays, solar cells, batteries, and photodetectors. Oxide electronics have a lot of potential because of their high carrier mobilities and ability to be manufactured at low temperatures. However, the preponderance of oxide semiconductors is n-type oxides, limiting present applications to unipolar devices and stifling the development of oxide-based bipolar devices like p-n diodes and complementary metal-oxide–semiconductors. We have contributed to oxide electronics, particularly on transition metal oxide semiconductors of which the cations include In, Zn, Sn and Ga. We have integrated these oxide semiconductors into thin film transistors (TFTs) as active channel layer in light of the unique combination of electronic and optical properties such as high carrier mobility (5-10 cm2/Vs), optical transparency in the visible regime (>~90%) and mild thermal budget processing (200-400°C). In this study, we achieved four different results. The first result is that unlike several previous reports on oxide p-n junctions fabricated exploiting a thin film epitaxial growth technique (known as molecular beam epitaxy, MBE) or a high-powered laser beam process (known as pulsed laser deposition, PLD) that requires ultra-high vacuum conditions, a large amount of power, and is limited for large-area processing, we demonstrate oxide-based heterojunction p-n diodes that consist of sputter-synthesized p-SnOx and n-IGZO of which the manufacturing routes are in-line with current manufacturing requirements. The second result is that the synthesized p-SnOx films are devoid of metallic Sn phases (i.e., Sn0 state) with carrier density tuneability and high carrier mobility (> 2 cm2/Vs). The third result is that the charge blocking performance of the metallurgical junction is significantly enhanced by the engineering of trap/defect density of n-IGZO, which is identified using photoelectron microscopy and valence band measurements. The last result is that the resulting oxide-based p-n heterojunction exhibits a high rectification ratio greater than 103 at ±3 V (highest among the sputter-processed oxide junctions), a low saturation current of ~2×10-10 A, and a small turn-on voltage of ~0.5 V. The outcomes of the current study are expected to contribute to the development of p-type oxides and their industrial device applications such as p-n diodes of which the manufacturing routes are in-line with the current processing requirements. 
    more » « less
  5. Over the two decades, amorphous oxide semiconductors (AOSs) and their thin film transistor (TFT) channel application have been intensely explored to realize high performance, transparent and flexible displays due to their high field effect mobility (μFE=5-20 cm2/Vs), visible range optical transparency, and low temperature processability (25-300 °C).[1-2] The metastable amorphous phase is to be maintained during operation by the addition of Zn and additional third cation species (e.g., Ga, Hf, or Al) as an amorphous phase stabilizer.[3-5] To limit TFT off-state currents, a thin channel layer (10-20 nm) was employed for InZnO (IZO)-based TFTs, or third cations were added to suppress carrier generations in the TFT channel. To resolve bias stress-induced instabilities in TFT performance, approaches to employ defect passivation layers or enhance channel/dielectric interfacial compatibility were demonstrated.[6-7] Metallization contact is also a dominating factor that determines the performance of TFTs. Particularly, it has been reported that high electrical contact resistance significantly sacrifices drain bias applied to the channel, which leads to undesirable power loss during TFT operation and issues for the measurement of TFT field effect mobilities. [2, 8] However, only a few reports that suggest strategies to enhance contact behaviors are available in the literature. Furthermore, the previous approaches (1) require an additional fabrication complexity due to the use of additional treatments at relatively harsh conditions such as UV, plasma, or high temperatures, and (2) may lead to adverse effects on the channel material attributed to the chemical incompatibility between dissimilar materials, and exposures to harsh environments. Therefore, a simple and easy but effective buffer strategy, which does not require any additional process complexities and not sacrifice chemical compatibility, needs to be established to mitigate the contact issues and therefore achieve high performance and low power consumption AOS TFTs. The present study aims to demonstrate an approach utilizing an interfacial buffer layer, which is compositionally homogeneous to the channel to better align work functions between channel and metallization without a significant fabrication complexity and harsh treatment conditions. Photoelectron spectroscopic measurements reveal that the conducting IZO buffer, of which the work function (Φ) is 4.37 eV, relaxes a relatively large Φ difference between channel IZO (Φ=4.81 eV) and Ti (Φ=4.2-4.3 eV) metallization. The buffer is found to lower the energy barrier for charge carriers at the source to reach the effective channel region near the dielectric. In addition, the higher carrier density of the buffer and favorable chemical compatibility with the channel (compositionally the same) further contribute to a significant reduction in specific contact resistance as much as more than 2.5 orders of magnitude. The improved contact and carrier supply performance from the source to the channel lead to an enhanced field effect mobility of up to 56.49 cm2/Vs and a threshold voltage of 1.18 V, compared to 13.41 cm2/Vs and 7.44 V of IZO TFTs without a buffer. The present work is unique in that an approach to lower the potential barrier between the source and the effective channel region (located near the channel/dielectric interface, behaving similar to a buried-channel MOSFET [9]) by introducing a contact buffer layer that enhances the field effect mobility and facilitates carrier supply from the source to the effective channel region. 
    more » « less