Ding, Caiwen, Ren, Ao, Yuan, Geng, Ma, Xiaolong, Li, Jiayu, Liu, Ning, Yuan, Bo, and Wang, Yanzhi. Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs. Retrieved from https://par.nsf.gov/biblio/10076776. Proceedings of the 2018 on Great Lakes Symposium on VLSI . Web. doi:10.1145/3194554.3194625.

Ding, Caiwen, Ren, Ao, Yuan, Geng, Ma, Xiaolong, Li, Jiayu, Liu, Ning, Yuan, Bo, & Wang, Yanzhi. Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs. Proceedings of the 2018 on Great Lakes Symposium on VLSI, (). Retrieved from https://par.nsf.gov/biblio/10076776. https://doi.org/10.1145/3194554.3194625

Ding, Caiwen, Ren, Ao, Yuan, Geng, Ma, Xiaolong, Li, Jiayu, Liu, Ning, Yuan, Bo, and Wang, Yanzhi. "Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs". Proceedings of the 2018 on Great Lakes Symposium on VLSI (). Country unknown/Code not available. https://doi.org/10.1145/3194554.3194625. https://par.nsf.gov/biblio/10076776.

@article{osti_10076776,
place = {Country unknown/Code not available}, title = {Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs}, url = {https://par.nsf.gov/biblio/10076776}, DOI = {10.1145/3194554.3194625}, abstractNote = {}, journal = {Proceedings of the 2018 on Great Lakes Symposium on VLSI}, author = {Ding, Caiwen and Ren, Ao and Yuan, Geng and Ma, Xiaolong and Li, Jiayu and Liu, Ning and Yuan, Bo and Wang, Yanzhi}, }