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1. INSPIRE: in - s torage p rivate i nformation re trieval via protocol and architecture co-design

   https://doi.org/10.1145/3470496.3527433  

   Lin, Jilan; Liang, Ling; Qu, Zheng; Ahmad, Ishtiyaque; Liu, Liu; Tu, Fengbin; Gupta, Trinabh; Ding, Yufei; Xie, Yuan (June 2022, Proceedings of the 49th Annual International Symposium on Computer Architecture)
2. CHIRP: C ompact and H igh-Performance FPGA Implementation of Un i fied Hardware Accelerators for R ing-Binary-LWE-based P QC

   https://doi.org/10.1145/3715153  

   Bao, Tianyou; He, Pengzhou; Fujimoto, Daisuke; Hayashi, Yuichi; Xie, Jiafeng (January 2025, ACM Transactions on Reconfigurable Technology and Systems)

   Post-quantum cryptography (PQC) has drawn significant attention from the hardware design research community, especially on field-programmable gate array (FPGA) platforms. In line with this trend, in this paper, we present a novel FPGA-based PQC design work (CHIRP), i.e.,Compact and high-Performance FPGA implementation of unIfied accelerators forRing-Binary-Learning-with-Errors (RBLWE)-basedPQC, a promising lightweight PQC suited for related applications like Internet-of-Things. The proposed accelerators offer flexibility across the available two security levels, thus expanding their application potential. In total, we presented four distinct hardware accelerators tailored to different performance and resource requirements, ranging from resource-constrained devices to high-throughput applications. Our innovation encompasses three key efforts: (i) we derived four optimized algorithms for RBLWE-ENC’s unified operation (covering the available two security levels), allowing flexible switching of security sizes while boosting calculations; (ii) we then presented the four novel accelerators (CHIRP) targeting FPGA platforms, featuring dedicated hardware structures; (iii) we finally conducted a comprehensive evaluation to validate the efficiency of the proposed accelerators on various FPGA devices. Compared to the existing unified design, the proposed accelerator demonstrated up to 91.4% reduction in area-delay product (ADP) on the Straix-V device. Even when compared with the state-of-the-art single security designs, the proposed accelerator (best version) obtains much better resource usage and ADP performance while unified operation (flexibly switching between two security levels) is considered on both AMD-Xilinx and Intel devices. We anticipate the findings of this research will foster advancements in FPGA implementation techniques for lightweight PQC development. 

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3. QUIDAM: A Framework for Qu ant i zation-Aware D NN A ccelerator and M odel Co-Exploration

   https://doi.org/10.1145/3555807  

   Inci, Ahmet; Virupaksha, Siri Garudanagiri; Jain, Aman; Chin, Ting-Wu; Thallam, Venkata Vivek; Ding, Ruizhou; Marculescu, Diana (September 2022, ACM Transactions on Embedded Computing Systems)

   As the machine learning and systems communities strive to achieve higher energy-efficiency through custom deep neural network (DNN) accelerators, varied precision or quantization levels, and model compression techniques, there is a need for design space exploration frameworks that incorporate quantization-aware processing elements into the accelerator design space while having accurate and fast power, performance, and area models. In this work, we present QUIDAM , a highly parameterized quantization-aware DNN accelerator and model co-exploration framework. Our framework can facilitate future research on design space exploration of DNN accelerators for various design choices such as bit precision, processing element type, scratchpad sizes of processing elements, global buffer size, number of total processing elements, and DNN configurations. Our results show that different bit precisions and processing element types lead to significant differences in terms of performance per area and energy. Specifically, our framework identifies a wide range of design points where performance per area and energy varies more than 5 × and 35 ×, respectively. With the proposed framework, we show that lightweight processing elements achieve on par accuracy results and up to 5.7 × more performance per area and energy improvement when compared to the best INT16 based implementation. Finally, due to the efficiency of the pre-characterized power, performance, and area models, QUIDAM can speed up the design exploration process by 3-4 orders of magnitude as it removes the need for expensive synthesis and characterization of each design. 

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4. CANNON: C ommunication- A ware Sparse N eural N etwork O ptimizatio n

   https://doi.org/10.1109/TETC.2023.3289778  

   Goksoy, A. Alper; Li, Guihong; Mandal, Sumit K.; Ogras, Umit Y.; Marculescu, Radu (January 2023, IEEE Transactions on Emerging Topics in Computing)

   Sparse deep neural networks (DNNs) have the potential to deliver compelling performance and energy efficiency without significant accuracy loss. However, their benefits can quickly diminish if their training is oblivious to the target hardware. For example, fewer critical connections can have a significant overhead if they translate into long-distance communication on the target hardware. Therefore, hardware-aware sparse training is needed to leverage the full potential of sparse DNNs. To this end, we propose a novel and comprehensive communication-aware sparse DNN optimization framework for tile-based in-memory computing (IMC) architectures. The proposed technique, CANNON first maps the DNN layers onto the tiles of the target architecture. Then, it replaces the fully connected and convolutional layers with communication-aware sparse connections. After that, CANNON optimizes the communication cost with minimal impact on the DNN accuracy. Extensive experimental evaluations with a wide range of DNNs and datasets show up to 3.0× lower communication energy, 3.1× lower communication latency, and 6.8× lower energy-delay product compared to state-of-the-art pruning approaches with a negligible impact on the classification accuracy on IMC-based machine learning accelerators. 

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5. HESSLE-FREE: He terogeneou s S ystems Le veraging F uzzy Control for R untim e Resourc e Management

   https://doi.org/10.1145/3358203  

   Moazzemi, Kasra; Maity, Biswadip; Yi, Saehanseul; Rahmani, Amir M.; Dutt, Nikil (October 2019, ACM Transactions on Embedded Computing Systems)