In electric vehicle systems, a high DC bus voltage is needed to be interfaced with a three-phase inverter to drive the electric motors or generators [1]- [3]. To step up the relatively low battery voltage to this higher DC busbar voltage, a dc-dc converter is often applied. Typical voltage ratings are 300 V input battery and 650 V DC bus [4]. This dc-dc converter not only regulates the bus voltage, but also protects the battery from over/under voltage, excessive charge/discharge currents [4]- [6]. A recent report from U.S. Department of Energy [7] estimates that by 2025, the power density of the electric traction drive system is supposed to exceed 100 kW/L based on 100 kW power level. This indicates the importance of a proper topology and optimized device and passive component design.
Traditional boost converter is a widely studied solution for this application. A 40 kW bidirectional dc-dc converter based on boost topology is designed in [8] with 6 kW/L power density working at 20 kHz switching frequency. However, it suffers from low efficiency and bulky reactive components. Also based on boost converter, a 3-phase interleaved converter with discrete inductors achieves a power density of 30.8 kW/L and 97.9% efficiency [9]. But the total inductor core volume is as bulky as about 1.3 Liters. To overcome this issue, constant frequency quasi square wave zero voltage switching (ZVS) converter is studied [10]. But it is inefficient at light load. Variable-frequency boundary mode quasi square wave ZVS control is applied in a 200 kW Si IGBT based prototype [4] to further increase the peak efficiency to 98%. However, the power density is only 6 kW/L. A 150 kW, 8.6 L interleaved boost dc-dc converter is designed with multiple DC sources [11]. But the power density is 17.44 kW/L, which is still low considering the above presented U.S. Department of Energy 2025 goal. Another commonly investigated topology for this application is flying capacitor multilevel converter (FCMC) [1][12]- [16]. Over 97% efficiency at 30 kW continuous operation is claimed in [1] by using FCMC with around 8.612 kW/L power density. However, it is difficult to realize a compact design considering the separate locations of the DCside resonant inductor and AC-side resonant capacitor. SiC MOSFET power modules have shown better performance compared with Si counterparts in high-power, high-frequency applications [17]- [20]. 1200 V 100 A SiC MOSFET power modules from Cree have been applied in a 60 kW dc-dc converter, which can achieve 20 kW/L power density [21]. But 75 kHz hard-switching operation doesn't fully utilize their advantages, which degrades overall 98.7% peak efficiency. These days, resonant switched capacitor converters are investigated for their modularity, high power density and high efficiency [15][22]- [25]. But the high-power applications of this group of topologies are not so well investigated, which needs to be compared fairly with other topologies.
Since different topologies use various voltage rating devices, it is challenging to compare the semiconductor die area usage among topologies. Dr. B. Jayant Baliga proposed a device-level index called figure of merit in [26], but it fails to evaluate the total device power loss among different topologies by using only on-resistance and the total gate charge. Total switching device power is defined in [27] using the product of switch voltage and current stresses as the evaluation method. But it is not able to indicate the optimized die area for different topologies. Relative total semiconductor chip area is proposed in [28], but it does not consider the relationship between total die area and the total device power loss. This paper will compare three dc-dc converter topologies and possible device candidates for this high-power electric vehicle application by using the proposed total semiconductor loss index. By utilizing SiC MOSFET power modules, a 100 kW 300 V -600 V one-cell STC prototype is built with ZCS achieved. The topology comparison, simulation and theoretical results, the designed prototype will be presented.
TOPOLOGY COMPARISON Fig. 1 shows the investigated three topologies, i.e. conventional boost converter, three-level flying capacitor multilevel converter (3-level FCMC) and one-cell switched tank converter (STC) with resonant inductor on the AC side. To evaluate the inductor and capacitor design differences, the corresponding resonant inductor current and voltage waveforms are shown in Fig. 2. The resonant capacitor voltage and current waveforms are presented in Fig. 3.
Multiple topologies such as boost converter, FCMC could achieve relatively high efficiency by selecting specific semiconductor die areas at the same power rating. But different from the boost converter, the FCMC and STC topologies utilize the devices with lower voltage rating. Thus, how to evaluate these topologies needs to be deliberated. To evaluate device technologies on converter topologies and relate the device power loss with the total die area usage so that minimal device power loss with an optimized die area can be achieved, the total semiconductor loss index (TSLI) is defined in Eq. (1).
are the functions of total die area. P cond * , P sw * are the corresponding loss normalized by output power P o . Normalized switching loss is further categorized into gate charge induced switching loss P Gate_charge * , turn-on and turn-off switching loss P turn_on * , P turn_off * .
In the ZCS operation, the switching loss could be estimated by the Coss discharged induced turn-on loss. So, the TSLI can be further shown in Eq. ( 2 (2) From Eq.(6.211) in [26], the device conduction loss is negatively proportional to the active die area. Hence, the device conduction loss can be expressed as Eq. (3) shows.
(3) Where, N is the number of active switches, I RMS_S(i) is the switch RMS current, R ds(on) is the switch on-resistance.
is the product of on-resistance and die area, determined by the device technology dependent coefficient ξ i and the voltage rating V B(i) . κ i is the die cutting factor ranging from 0 to 1, reflecting different cutting strategies for the dies used by specific switches. The sum of each κ i equals to 1.
According to Eq.( 6.211) in [26], when the die area is enlarged, the input capacitance increases, which means larger gate current is needed to charge the input capacitor and thus increases the gate charge induced switching loss, which is presented in Eq. ( 4).
(4) Where, f s is the switching frequency. Q g is the total gate charge. V gs is the difference of the maximum and minimum gate-source voltages. β i is the total gate charge per die area, dependent on the device technology. Besides, turn-on and turnoff switching losses are explained in Eq. ( 5) and ( 6), respectively. The turn-on energy E on and turn-off energy E off are functions of turn-on and turn-off drain current.
(5) (6) The output capacitance C oss discharge induced turn-on switching loss is part of the total turn-on switching loss. From Page 409 in [26], the gate-drain capacitance C gd increases with the die area. From Eq.(6.174), (6.175), (6.178) in [26], the drain-source capacitance C ds is positively proportional to the junction area. Thus, C oss (equal to C gd + C ds ) discharge induced turn-on switching loss is positively related to the die area. The C oss induced turn-on switching loss is shown in Eq. ( 7). (7) Where, V ds is drain-source voltage. γ i is the device output capacitance per die area, which is dependent on the device technologies as well. For a specific circuit topology, when the output power and switching frequency are fixed, theoretically it is possible to derive an optimum die area for each switch to achieve the minimized total device power loss. In other words, when the total device power loss is the same between two topologies under specific conditions, the one with smaller total die area can achieve more efficient die utilization. These two different evaluation perspectives based on the above SLI parameter can provide more comprehensive understandings between the total device power loss and semiconductor die area.
In this comparison, the boost converter is assumed to operate at continuous conduction mode and the inductor current ripple is 30% of its average current. Thus, the device turn-on and turn-off losses are considered. 3-level FCMC and one-cell STC are designed to operate at ZCS mode and the device power loss of these two is the same. Coss losses are included in the switching losses of the switches in the one-cell STC.
Since the voltage rating of the switches in the boost converter is twice the voltage stress (2×600 V), only the dies with 1200 V voltage rating are considered, which are S4103 and CPM2-1200-0025B. The turn-on and turn-off power loss of S4103 are derived from the switching energy vs. drain current curve in the datasheet of Rohm 1200 V SCT3022KL SiC MOSFET since it shares the same on-resistance and current rating information with the S4103 die. While the turn-on and turn-off power loss of CPM2-1200-0025B are derived from the switching energy vs. drain current curve in the datasheet of Cree 1200 V C2M0025120D SiC MOSFET since it shares the similar on-resistance and current rating information with the CPM2-1200-0025B die.
Total semiconductor power loss is compared in Fig. 4. With the same total die area, one-cell STC achieves lower total semiconductor power loss compared with boost converter due to higher switching loss of the boost converter.
Compared with 3-level FCMC, one-cell STC can achieve better device clamping and allow the converter to be designed in a more compact way because the inductor is on the AC side. Thus, one-cell STC is selected in this paper.
TSLI can also reflect the relationship between the total device power loss and the output power. Fig. 5(a) and (b) show the TSLI vs. the total converter die area with different output power of boost converter and one-cell STC, respectively, at 100 kHz switching frequency. Based on the TSLI comparison results in Fig. 4, the Cree 1200 V CPM2-1200-0025B SiC die performs best in boost converter and the Cree 900 V CPM3-0900-0010A SiC die works most effectively in the one-cell STC topology. Thus, in the below evaluation, these two SiC dies are selected for the corresponding topologies. In different output power, the boost converter inductor current ripple is maintained as 30% the average current [29]. As the output power increases, the TSLI of both the two topologies decreases, which indicates smaller total device loss at the same converter die area usage.
Besides, the proposed TSLI can be also used to present the impact of the switching frequency on the total device power loss. Fig. 6(a) and (b) illustrate the TSLI vs. the total converter die area with different switching frequency of boost converter and one-cell STC, respectively, at 100 kW output power. When the switching frequency increases, the TSLI of both the two topologies increases as well, which indicates larger total device power loss at the same converter die area usage.
The theoretical efficiency and power loss breakdown are estimated in Fig. 7. The conduction loss has been calculated considering two additional aspects. One is the fact that onresistance increase with the temperature rise. The other is the deadtime induced switch RMS current increase.
A 300 V 600 V 100 kW one-cell STC operated at ZCS is simulated in PLECS. The simulation results are shown in Fig. 8 with the switching frequency tuned to 96 kHz and the deadtime set as 300 ns. From Fig. 8(b), the switch current I d decreases to zero before the drain-source voltage V ds starts to rise. Thus, ZCS turn off has been achieved.
A prototype has been built as shown in Fig. 9. Fig. 9(a) shows the 3-D layout model designed in Solidworks. The resonant tank is on the left-hand side, which is composed of three polypropylene film resonant capacitors, one soft-ferrite core inductor with one-turn copper foil winding. The SiC power module is mounted on a water-cooling heatsink. The right-hand side presents the DC capacitors and the 2-layer DC busbar, which includes V in , V o and ground DC busbars. An assembled 100 kW prototype is shown in Fig. 9(b). The power density has been measured as around 42 kW/L.
This paper utilizes a resonant switched capacitor based onecell switched tank converter in a 300 V -600 V 100 kW variable voltage converter for the electric vehicle applications. The topology has been proved to be more efficient and compact compared with boost converter and three-level flying capacitor multilevel converter. A new index called total semiconductor loss index has been proposed to evaluate topologies and device technologies at customized output power and switching frequency. The one-cell STC can achieve lower device power loss with the same die area usage compared with boost converter. In other words, the one-cell STC utilizes smaller die area with lower device manufacturing costs at the same device power loss. The theoretical efficiency and power loss breakdown analysis has been conducted. The simulation results at the ZCS operation are presented. The estimated efficiency is about 99.2% at 30 kW, 99.13% at half load, and 98.64% at full load. Both the 3-D and real protypes have been presented, which shows a power density of around 42 kW/L. More design details and test results will be presented in future publications.