Commercialized photovoltaic technologies today such as CdTe and multicrystalline Si as well as emerging technologies such as halide perovskites are built from polycrystalline materials having abundant grain boundaries. Cadmium Telluride (CdTe) has emerged as the leading commercial thin film photovoltaic (TFPV) technology in the past 10 years, has a direct band gap of 1.5 eV, and can exhibit radiative-limited minority carrier lifetime comparable with GaAs. [1][2][3] The fact that CdTe is a binary semiconductor allows near-stoichiometric thin film layers to be deposited rapidly and at low cost. Devices are typically 2-5 µm thick primarily because of doping limitations, whereas thinner devices could be manufactured more rapidly.
Recently, champion cell efficiency greater than 22% and module efficiency greater than 18% have been demonstrated for polycrystalline (px) CdTe solar cells. [4,5] . These results have been attributed to reductions in parasitic light absorption in the buffer layer and alloying with Se reduces the minimum bandgap, both of which increase the short circuit current (JSC). [6,7] While open circuit voltages (VOC) above 1 V have been demonstrated for single crystalline (sx) CdTe devices, the VOC of most polycrystalline devices remains stubbornly below approximately 850-900 mV. [8] The substantial gap between VOC in monocrystalline and polycrystalline devices is in large part caused by grain boundaries (GBs), which have significant non-radiative recombination velocity.
While a great deal of work has sought to understand grain boundaries, it is clear that there are many variations amongst them that are not well understood and studied in detail. [9][10][11][12][13][14][15] Better understanding of all sources of recombination, generation and FF losses, especially those related to planar defects and interfaces in thinner devices, is essential to enable further advancements. Increasing VOC towards the detailed balance limit of 1.247 V for AM1.5 spectrum in thinner, higher-doped devices while maintaining high JSC and fill factor (FF) which are critical challenges for advancing CdTe photovoltaic module technology. [1,16] In this work, we report that the commonly used bromine etching based processing step in laboratory device fabrication leads to losses in device efficiency through composition changes extending deep into the CdTe absorber layer that may be limiting laboratory devices to an empirical limit seen from many non-commercial groups over the past decades of roughly 14-16% efficiency.
CdTe polycrystalline thin film solar cells are typically fabricated in a superstrate configuration with n-type transparent conductive oxide, n-type buffer layer, and the p-type CdTe absorber layers deposited sequentially on glass. In superstrate cells light enters through the glass defining this side as the "front" of the cell. The formation of Ohmic, low resistance "back" contacts to the p-type CdTe is a stubborn materials and fabrication challenge -without special fabrication procedures a high Schottky barrier forms and degrades cell performance. An additional challenge is that GBs in px-CdTe devices introduce recombination centers thereby reducing the carrier lifetime in the absorber layer. This leads to increased dark current and low Voc and hence reduced power conversion efficiency. The standard CdTe cell technology relies on an "activation" process of annealing in Cl to passivate grain boundaries and point defects. [17][18][19][20][21] Etching of the CdTe back surface prior to contact deposition using bromine (e.g. Br in methanol) or oxidizing acids (e.g. nitric-phosphoric mixtures) has been widely used. This serves to produce a Te-rich layer at the back surface and in many cases to also remove residues from the Cl activation process. [11,[22][23][24][25][26][27][28][29][30][31] Shallow etching of CdTe, specifically processes that selectively remove Cd, are typically used. Additionally, etching can help in forming better Ohmic contacts and thus has been widely used. Previous studies have shown that chlorine treatment results in depletion regions around GBs and being Cd and Cl rich. [12,13,32] However, these measurements were made on grain boundaries deeper inside the CdTe layer before any chemical etching was carried out. Thus, the details at the CdTe-back contact interface required for making good Ohmic contact, following Br:MeOH etching, is not completely understood.
Herein, we detail previously-unobserved changes in grain boundary composition near the back surface of CdTe device films induced by an etching process widely-used for device fabrication.
Using scanning transmission electron microscopy (STEM) based composition analysis from energy dispersive x-ray spectroscopy (EDS), we find that Cd is depleted from the GBs at their intersection with the free surface to depths of up to 1.5-2 µm. Cd depletion at GBs is influenced by their crystallography, i.e. randomly oriented versus coincident site lattice (CSL). This study adds to the existing body of knowledge on materials and microstructure for photovoltaic and other energy applications; the general insight being that grain boundary stoichiometry may not be uniform, so neither will be their electronic structure nor electronic properties. Twodimensional (2D) device simulations show that such variation in GB properties along their length produces effects on devices impossible to capture within the typical one dimensional (1D) analytical or computational device models. This powerful combination of experiment and simulation demonstrates that, while within a 1D device model additive (e.g. evaporation of Te or ZnTe) and subtractive (e.g. Br etching) methods nominally produce the same device stack having a layer of Te at the back contact and thus device operation, the reality of different 3D microstructures induced by additive and subtractive back contact processes have significant effects on device performance. Importantly, our findings indicate that in this case of subtractive etching of the back contact for CdTe devices may be limiting many current devices and surely will for future device generations. This is because of the increased recombination activity near the back contact in cases where greater numbers of minority carriers reach the back contact by virtue of increased minority carrier diffusion length or decreased absorber thickness. In contrast, additive deposition of a back contacting layer that does not restrict quasi-Fermi level splitting does not affect grain boundaries and is compatible with future thinner, higher efficiency devices, demonstrated by the recent record devices in the literature. [6,7] Detailed understanding of the 2D and 3D variation of grain boundary composition, structure, and properties is required to further understand and improve photovoltaic and other technologies using multicrystalline and polycrystalline layers.
Lamella from CdTe device stacks were lifted out using a well-developed focused ion beam (FIB) process and characterized using transmission electron microscopy (TEM) to reveal the nanoscale structure and chemistry of the grains and grain boundaries. twinning appear as alternating stripes of color within grains. Different regions of interest were selected for nanoscale STEM EDS characterization to determine the qualitative to semiquantitative chemistry of grain boundaries and features in the material. Regions including the intersection of grain boundaries with the back surface and regions of the same grain boundaries deeper in the bulk of the CdTe layer were imaged and chemically mapped. The areas surrounding the intersection of many GBs with the back surface of the CdTe (which becomes the back p-type contact in devices) were analyzed for their nanochemistry. Two regions of interest (ROIs) are indicated as black boxes in Figure 1 and illustrate the main findings. ROI 1 contains a randomly-oriented GB and ROI 2 contains a ∑5 coincident site lattice (CSL) GB. The Cd concentration is significantly lower in both the randomly-oriented and ∑5 grain boundaries than in the adjacent CdTe grains in the region near the free surface that was thus exposed to Br etching. In the Cd maps from both ROIs, the grain boundaries are clearly darker than the grains on either side, thus it is clear that the net Cd concentration is notably lower in both grain boundaries than in the surrounding CdTe grains. surface (which becomes the p-type contact) into a CdTe grain. These were produced by integrating horizontally within the dashed analysis box as shown in Figure 2c and 2d. The Te signal begins to rise approximately 3 nm before the Cd signal, indicating that Cd has been selectively etched from the CdTe at the back surface of CdTe. This is the desired outcome of such Br etching -to selectively remove Cd leaving behind a Te-rich or even elemental Te layer (depending on the etching conditions) in order to form a better p-type Ohmic back contact. In a 1D model of a CdTe solar cell, this would appear as either a highly p-type doped CdTe layer or a conformal layer of Te. However, we discovered additional details of the effects of Br etching that 1D models are completely unable to capture. The apparent high counts near the Figure 3. (A) Integrated STEM-based EDS chemical composite linescans for Cd and Te at the back surface of CdTe in region 2 reported in Figure 1. The inset shows the line profile deeper into the bulk of the grain. STEM-EDS chemical composite maps (B) Cd and (C)Te of the areas used for the line scan. Note the chemical compositions are reported based on standardless kfactor quantification, where the input parameters are taken as 200 keV electron beam with a minimum nominal thin foil thickness of a 100 nms and reported in net counts. Standard deviations are quantified based on normalized statistical distribution along the scan direction. adjacent grains. From the net count EDS maps, we calculated and compared the relative Cd and
Te compositions for each of the grains adjacent to the random and symmetric GBs. The Cd concentration in the GB region of is 3.8 atomic % lower than the two adjacent grains. This is statistically significant compaed to the primary source of error, the uncertainty for measuring the relative concentration of Cd based on L-emission x-ray lines, which is estiamted to be ± 0.81 at%. ROIs 3 and 4 (Figure S1) are exemplary net count maps taken from the continuation of the GB in ROI 1 into the film at a GB triple junction near the middle of film and close to the CdTe / CdS interface. No such variation in Cd chemistry is observed at the GB regions here.
This implies that the Cd has been selectively removed out of the GB regions in ROI 1 and 2 as a result of bromine etching. No statisitcally significant change in Te concentration is observed within this random grain boundary compared to the adjacent grains. This GB and the surrounding grains appear to be CdTe within 4 at% (few times 10 20 /cm 3 ) levels of Cd vacancies (VCd). VCd introduces an acceptor state and a deeper trap state when isolated, as well as facilitating the formation of CuCd acceptors upon intorduction of Cu in back contact processing steps. Br etching leaches Cd preferentailly from the CdTe grains' free surfaces as well as aggressively from grain boundaries intersecting the back surface. Since GB diffusion is in almost all cases faster than bulk diffusion, the remarkable depths over which Cd is depleted can be understood. Thus, the electrical back contact effectively is extended conformally down the grain boundaries. In thinner cells however, this could lead to shorting and increased recombination.
The case of CSL boundaries such as the ∑5 GB shown in Figure 2c and 2d is slightly different and ultimately has more significant device implications. Figure 5 shows similar linescan analyses of Cd and Te profiles. The loss of Cd referenced to the adjacent grains is more pronounced and persists over a significantly wider distance laterally into the device. Also the Te counts are higher than in the adjacent grains, while no increase in Te was observed at random GBs. Since our understanding of the Br etching process is that it removes Cd but does not add Te, we speculate that the CSS deposition process results in Te-enriched ∑5 GBs compared to grains. Following this specific CSS process of CdTe thin film growth, many grain boundaries are enriched in Te in the vicinity of the back surface compared to the adjacent CdTe grains. However, we do see evidence of Kirkendall voiding (Figure 6A) as a result of Cd removal and the Te remaining in the GB region agglomerating to form pure Te, which may also produce increased Te counts depending which we intend to address in future work. These compositional analyses and STEM imaging indicate that CSL GB regions exposed to the Br etching have in fact converted to elemental Te -the CdTe lattice apparently collapses upon the removal of some threshold of Cd.
Without Cl treatment, device performance and effective minority carrier lifetime suffer deleteriously. After treatment, Cl is observed within grains but tends to accumulate especially in GBs [17][18][19][20] . Figure 6 shows the measured distribution of Cd, Te and Cl over the same 46.5° randomly-oriented grain boundary region at the back surface of CdTe shown in Fig. 2. While the Cl signal is somewhat noisy, it is clear that it is lower along the GB where Cd was removed.
Cl in the region of the GBs affected by etching suggests that both charge density and recombination velocity in this region should be higher. It is a surprising finding that the etching of Cd was more pronounced along the symmetric grain boundaries examined compared to random ones. We suspect the reason for the reported differences in chemistry is the differential etching rate of the back surface of CdTe between non-symmetric and symmetric grain boundaries. At random grain boundary, the non-symmetric interface patterning contains a significant portion of non-parallel components to the surface. At symmetric grain boundaries, there are number of oriented units with well aligned directions that contain a number of preferred unit cell directions. Therefore, the atomic line density for preferred orientations is lower than in random cases. This low angle higher symmetry grain boundary, such as coincident site lattice Σ-type, on the other hand offers a significant improvement in the atomic arrangement and thus leads to a lower degree of complexity for etching away material. This observation of nanochemistry varaition at the back surface and grain boundary core explains how a chemical etching step forms a Te rich surface, which aids in formation of an Ohmic back contact. However, the Te layer is formed as a result of chemical etching by removal of Cd 2+ cations. This implicates that this region has a higher cadmium vacancy (VCd) which is detrimental to carrier recombination lifetimes. So there are two counter-acting processes, an ntype Te layer, which aids in carrier screening and improves carrier collection at the back surface and a defect rich VCd region which reduces recombination lifetime. Therefore, it is essential to understand the effect of this variation in nanochemistry on device performance.
In order to independently vary the effects of the multiple changes in composition induced by the Br etching within the near-surface regions of GBs and the differences between symmetric and random boundaries, we utilized the benchmarked 2D drift-diffusion-Poisson device simulation with accepted baseline material parameters found in literature and refined the doping, GB recombination velocity, and bulk lifetime to reasonably match representative devices fabricated in the manner as the samples from which the lamella were prepared. [33,34] We focus here on trends in the simulated behavior as devices with macroscopic area contain computationintractablly large numbers of different grains and grain boundary properties. Polycrystalline devices will manifest behaviors corresponding to mixtures of these base cases (and perhaps others we have not considered), thus allowing us to extrapolate to real-world observations. Four important scenarios were investigated; (1) a device with no GBs which is thus 1D, (2) GBs with uniform properties through the CdTe thickness with Te contacting layer deposited, (3) the random GB case in which the etch-affected GB core is unpassivated, adjacent grain border regions are higher p-type doped CdTe, and an etch-produced Te contacing layer covers the back surface, and (4) the symmetric case in whcih the GB core and border regions are converted to elemental Te and an etch-produced Te layer covers the back surface. Table 1 and Figure 7 show the simulated device performance metrics and current voltage characterstics respectively. Compared to the case of having a GB with a deposited Te contact layer, both symmetric and random GBs etched near the back contact result in reduced solar cell performance. However, the symmetric case in which Cd is etched to the extent that tens of nm surrounding the GB convert to elemental Te is the most harmful to Voc and efficiency. Amongst the large number of CdTe solar cells that have been fabricated in research labs using Br etching or other similar aggressive etchants (e.g nitric-phosphoric etch) it is no coincidence that to our knowledge these solar cells have not exceeded approximately 16% efficiency. The impacts of etching-induced GB composition changes will only be more drastic in devices with thinner absorber layers or increased minority carrier diffusion length such that increased concentrations of minority carriers may encounter grain boundary regions near the back contact.
In this work, we use the specific example of chemical etching of grain boundaries near the back contact of CdTe solar cells to illustrate the broader implications of nanoscale variations in composition and thus properties of polycrystalline CdTe. We found that the bromine etching step widely used in research community to produce a Te back contacting layer can be limiting to CdTe solar cell device performance. For symmetric GBs, we find conversion to narrow-gap elemental Te while for both symmetric and random GBs this process also removes chlorine thus eliminating its passivation of GB electronic states. The simulated results of these effects on device performance demonstrate that Te rich grain boundaries created as a secondary consequence of Br:MeOH etching, limit device efficiency.
Largely, the results of this study indicate that contrary to current established processes, chemical etching to create a Te rich back surface in CdTe thin film solar cells is deleterious to device performance. This suggests that an additive method of Te deposition is better for device efficiency as it would preserve the chemistry at the grain boundaries near the back surface of CdTe. From a more general perspective, this shows the potential for this new paradigm to provide improved understanding of most of the leading photovoltaic materials used by researchers and industry today.
Material and Device Fabrication: Glass substrate is used to deposit the CdTe polycrystalline thin films. The substrate is cleaned by a brief etching in dilute hydrofluoric acid. A 300 nm layer of ITO is deposited on the glass by RF sputtering. A 60-100 nm CdS layer is grown on top of ITO layer by chemical bath deposition process. After a heat treatment of the CdS layer, closed space sublimation is used to deposit a 3-5 µm thick CdTe layer. This is followed by an annealing step in presence of CdCl2 to passivate the grain boundaries and enhance the opto-electronic properties of CdTe. This is followed by a bromine-methanol etching (0.1% by volume) process. Electron Microscopy Characterization: Analytical transmission electron microscopy was performed on the JEOL 2800. High-resolution EDS chemical imaging was performed on a JEOL 2800 in STEM mode at 200 kV using two windowless, close coupled silicon drift energy dispersive X-ray spectroscopy (EDS) detectors. At each pixel, a complete spectrum including the Cd and Te L emission peaks was obtained with the best achievable spatial resolution for the microscope consistent with the specimen thickness. Spectral image acquisition was performed by accumulating a series of consecutive sub-second frames with drift correction between frames and a total acquisition time of greater than 40 minutes. The EDS data were then processed using Thermo-Scientific Image Analysis software to extract principal components describing individual phases. Essentially, the pixel-by-pixel spectra for each image were decomposed into basis sets corresponding to stoichiometric CdTe, Cd-poor CdTe, and Cd-rich CdTe. To generate EDS chemical maps, the x-ray emission spectra were quantified after subtracting the background and each of the elements (Cd, Te) were calculated based on calibrated k-factors. [35] The analytical certainty associated with this EDS profiling is estimated to be within 3 atomic % depending on background and overlap of elemental peaks. To resolve the atomic lattice and structure, high-resolution transmission electron STEM micrographs were obtained and analyzed. At 200 kV, a 1 nm sized e-beam probe is precessed at 0.4°. Based on the sample interaction with the probe, a diffraction pattern is generated at each pixel (5 nm pixel size). A total of 5 precessions are performed at each pixel. Based on the collected diffraction pattern at each pixel an inverse pole figure was constructed using the EDAX TSL commercial software.
This inverse pole figure reports the orientation of grains based on an input CdTe cubic crystal structure file from the Inorganic Crystal Structure database (Figure 1).
Device Modelling: Since current available techniques of CdTe growth don't allow for tuned symmetric or random grain boundary oriented growth, 2D device modeling by TCAD Synopsys Sentaurus was used to simulate the effect of Br:MeOH etching on device performance. Three different cases were studied corresponding to etching effects on symmetric grain boundary orientation, random grain boundary orientation and no etching of back surface with a Te layer deposition. To understand the effects of these geometries on device performance. A 1D standard CdTe device was also modelled as a standard reference comparison [33,34] . Figure S2