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Title: Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V
RISC-V is a promising open source architecture that targets low-power embedded devices and SoCs. However, there is a dearth of practical and low-overhead security solutions in the RISC-V architecture. Programs compiled using RISC-V toolchains are still vulnerable to code injection and code reuse attacks such as buffer overflow and return-oriented programming (ROP). In this paper, we propose two hardware implemented security extensions to RISC-V that provides a defense mechanism against such attacks. We first employ a Physically Unclonable Function (PUF)-based randomized canary generation technique that removes the need to store the sensitive canary words in memory or CPU registers, thereby being more secure, while incurring low overheads. We implement the proposed Canary Engine in RISC-V RocketChip with Rocket Custom Coprocessor (RoCC). Simulation results show 2.2% average execution overhead with a single buffer protection, while a 10X increase in buffer count only increases the overhead by 1.5X when protection is extended to all buffers. We further improve upon this with a dedicated security coprocessor FIXER, implemented on the RoCC. FIXER enforces fine-grained control-flow integrity (CFI) of running programs on backward edges (returns) and forward edges (calls) without requiring any architectural modifications to the processor core. Compared to software-based solutions, FIXER reduces more » energy overhead by 60% at minimal execution time (1.5%) and area (2.9%) overheads. « less
Authors:
; ; ;
Award ID(s):
1801534 1821766 1814710 1723687 1718474
Publication Date:
NSF-PAR ID:
10163937
Journal Name:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Page Range or eLocation-ID:
1 to 1
ISSN:
0278-0070
Sponsoring Org:
National Science Foundation
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