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			<titleStmt><title level='a'>Two-Dimensional/Three-Dimensional Schottky Junction Photovoltaic Devices Realized by the Direct CVD Growth of vdW 2D PtSe &lt;sub&gt;2&lt;/sub&gt; Layers on Silicon</title></titleStmt>
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				<publisher></publisher>
				<date>07/16/2019</date>
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				<bibl> 
					<idno type="par_id">10176619</idno>
					<idno type="doi">10.1021/acsami.9b09000</idno>
					<title level='j'>ACS Applied Materials &amp; Interfaces</title>
<idno>1944-8244</idno>
<biblScope unit="volume">11</biblScope>
<biblScope unit="issue">30</biblScope>					

					<author>Mashiyat Sumaiya Shawkat</author><author>Hee-Suk Chung</author><author>Durjoy Dev</author><author>Sonali Das</author><author>Tania Roy</author><author>Yeonwoong Jung</author>
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			<abstract><ab><![CDATA[Two-dimensional (2D) platinum diselenide (PtSe 2 ) layers are a new class of near-atom-thick 2D crystals in a van der Waalsassembled structure similar to previously explored many other 2D transition-metal dichalcogenides (2D TMDs). They exhibit distinct advantages over conventional 2D TMDs for electronics and optoelectronics applications such as metallic-to-semiconducting transition, decently high carrier mobility, and low growth temperature. Despite such superiority, much of their electrical properties have remained mostly unexplored, leaving their full technological potential far from being realized. Herein, we report 2D/three-dimensional Schottky junction devices based on vertically aligned metallic 2D PtSe 2 layers integrated on Si wafers. We directly grew 2D PtSe 2 layers of controlled orientation and carrier transport characteristics via a low-temperature chemical vapor deposition process and investigated 2D PtSe 2 /Si Schottky junction properties. We unveiled a comprehensive set of material parameters, which decisively confirm the presence of excellent Schottky junctions, i.e., high-current rectification, small ideality factor, and temperature-dependent variation of Schottky barrier heights. Moreover, we observed strong photovoltaic effects in the 2D PtSe 2 /Si Schottky junction devices and extended them to realize flexible photovoltaic devices. This study is believed to significantly broaden the versatility of 2D PtSe 2 layers in practical and futuristic electronic devices.]]></ab></abstract>
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<div xmlns="http://www.tei-c.org/ns/1.0"><head>&#9632; INTRODUCTION</head><p>Two-dimensional (2D) transition-metal dichalcogenides (TMDs) are a group of compounds in the form of MX 2 , (M: transition metals, X: chalcogens) assembled by weak van der Waals (vdW) bonding exhibiting exotic optical and electrical properties. Among them, molybdenum-(Mo) and tungsten (W)-based disulfides (MoS 2 and WS 2 ) or diselenides (MoSe 2 and WSe 2 ) have gained significant interest in the recent developments of 2D TMDs. <ref type="bibr">[1]</ref><ref type="bibr">[2]</ref><ref type="bibr">[3]</ref><ref type="bibr">[4]</ref><ref type="bibr">[5]</ref><ref type="bibr">[6]</ref><ref type="bibr">[7]</ref> Generally semiconducting in nature, 2D TMDs exhibit enhanced light-matter interaction and band-gap tunability with varying 2D layer numbers projecting exciting applications in electronics and optoelectronics. <ref type="bibr">[8]</ref><ref type="bibr">[9]</ref><ref type="bibr">[10]</ref> Moreover, they present extraordinary mechanical flexibility in comparison to traditional thin-film inorganic semiconductors, rendering vast opportunities toward devising futuristic devices of unconventional forms. <ref type="bibr">10,</ref><ref type="bibr">11</ref> Despite such advantages, some critical limitations concerning their material properties and preparation methods hinder their widespread utilization for practical technologies. For instance, their carrier mobilities are inferior to those of traditional semiconductors (e.g., silicon or III-V compounds), <ref type="bibr">4,</ref><ref type="bibr">8,</ref><ref type="bibr">9</ref> which further degrade when they are synthetically grown via scalable routes such as chemical vapor deposition (CVD). <ref type="bibr">12,</ref><ref type="bibr">13</ref> Recently, a new type of 2D crystals based on noble metals such as platinum (Pt) has been discovered, which includes PtSe 2 , PtS 2 , and PtTe 2 . <ref type="bibr">[14]</ref><ref type="bibr">[15]</ref><ref type="bibr">[16]</ref> Among them, 2D PtSe 2 is particularly gaining increasing attention due to distinguishable property advantages over Mo-or W-based 2D TMDs. First, its theoretically predicted carrier mobility at room temperature is &gt;1000 cm 2 /(Vs), <ref type="bibr">17,</ref><ref type="bibr">18</ref> which is much higher over 2D MoS 2   19   and is even comparable to black phosphorus (BP). <ref type="bibr">18,</ref><ref type="bibr">20,</ref><ref type="bibr">21</ref> Unlike BP, which is prone to very rapid air oxidation and its associated property degradation, 2D PtSe 2 is highly stable in ambient conditions. <ref type="bibr">18,</ref><ref type="bibr">22</ref> More interestingly, it presents a sizedependent transition of carrier transport properties with a dimensional reduction from bulk to monolayer; i.e., 2D PtSe 2 of large layer number exhibits strong metallic carrier transport, <ref type="bibr">15,</ref><ref type="bibr">20,</ref><ref type="bibr">23</ref> which transitions to semiconducting as it gets close to mono-or a few layers. Recently, developed CVD strategies employing the thermal selenization of elemental Pt have yielded the growth of 2D PtSe 2 layers at 400 &#176;C, <ref type="bibr">[24]</ref><ref type="bibr">[25]</ref><ref type="bibr">[26]</ref> much lower than what has been demanded for the growth of Mo-or W-based 2D TMDs. <ref type="bibr">2,</ref><ref type="bibr">27,</ref><ref type="bibr">28</ref> Despite these proven property and manufacturing advantages uniquely inherent to 2D PtSe 2 layers, much of their electrical properties have remained largely unexplored, leaving their full technological potential far from being realized. For example, the strong metallic nature of 2D PtSe 2 layers projects metal/semiconductor Schottky junction based on "mixed-dimensional" vdW heterostructures <ref type="bibr">29</ref> when they are interfaced with threedimensional (3D) semiconductors. The most well-established form of 2D/3D vdW heterostructure-based Schottky junctions can be found in graphene/semiconductor heterojunctions such as mechanically integrated graphene on top of silicon (Si). Although these graphene/Si Schottky junctions are recently gaining significant interest in a variety of electronic applications such as photovoltaic devices, <ref type="bibr">30,</ref><ref type="bibr">31</ref> their preparation requires the mechanical separation of high-temperature CVDgrown graphene from growth substrates (e.g., copper (Cu)) and its subsequent transfer to Si wafers. <ref type="bibr">[32]</ref><ref type="bibr">[33]</ref><ref type="bibr">[34]</ref> Accordingly, the process stands a high chance of introducing unwanted contamination throughout the chemical/mechanical treatment of graphene for delamination and integration.</p><p>In this article, we demonstrate 2D/3D vdW heterostructurebased Schottky junctions of mixed dimensionality by combining 2D PtSe 2 layers with 3D Si substrates. We directly grew metallic 2D PtSe 2 layers on lightly doped Si wafers at 400 &#176;C and investigated Schottky junction properties. We verified a comprehensive set of material parameters, which define excellent Schottky junction characteristics, i.e., small ideality factor, large current rectification, and temperature-dependent variation of Schottky barrier heights. Moreover, we observed strong photovoltaic effects in these 2D PtSe 2 /3D Si Schottky junction devices.</p></div>
<div xmlns="http://www.tei-c.org/ns/1.0"><head>&#9632; RESULTS AND DISCUSSION</head><p>Figure <ref type="figure">1</ref> describes the schematic of a 2D PtSe 2 /3D Si Schottky junction device and its associated fabrication process steps. Figure <ref type="figure">1a</ref> illustrates that the device is composed of 2D PtSe 2 layers intimately interfaced with a patterned Si wafer contacted with gold (Au) electrodes. Two-dimensional PtSe 2 layers are directly grown on Si in a vertical orientation via the CVD selenization of Pt as previously reported. <ref type="bibr">35</ref> Figure <ref type="figure">1b</ref> shows the step-by-step procedure to fabricate a 2D PtSe 2 /Si Schottky junction device. A lightly doped Si wafer is selectively deposited with silicon dioxide (SiO 2 ) through a shadow mask by electron beam evaporation (deposition rate: &#8764;0.5 &#197;/ s), which defines an open Si area of 0.25 cm 2 . Pt film of controlled thickness is deposited by electron beam evaporation (deposition rate: &#8764;0.1 &#197;/s) through another shadow mask, resulting in both Pt/Si (active area) and Pt/SiO 2 (electrode area) interfaces. The prepared Pt-deposited Si wafer is placed in the center of a quartz tube CVD furnace with a preloaded alumina boat containing selenium powders at the furnace upstream side. The CVD furnace is pumped down to a base pressure of &#8764;1 mTorr, followed by purging with argon (Ar) gas to remove any residual impurities inside the quartz tube. Subsequently, it is heated up to 400 &#176;C in 50 min for a dwell time of 50 min under a continuous flow of Ar gas. After the CVD reaction, the furnace is naturally cooled down to room temperature, and the conversion of Pt to 2D PtSe 2 layers is confirmed by a noticeable color change in the Pt-deposited area. Finally, the top and bottom Au electrodes are deposited on the top (2D PtSe 2 /SiO 2 ) and the bottom (bare Si) sides of the wafer, respectively. Figure <ref type="figure">1c</ref> shows a photograph image of a complete 2D PtSe 2 /Si Schottky junction device. It is worth mentioning that the low growth temperature of 400 &#176;C for 2D PtSe 2 layers is comparable to the thermal budget back-end-ofline temperature adopted in complementary metal-oxide semiconductor (CMOS) processes, <ref type="bibr">36</ref> indicating potential advantages of CMOS-compatible large-scale manufacturing.</p><p>Microstructures and atomic-bonding natures of the 2D PtSe 2 layers directly grown on Si wafers were characterized by transmission electron microscopy (TEM) and Raman spectroscopy. We have previously identified that two distinguishable 2D layer orientations of horizontal and vertical can be achieved by CVD-selenizing Pt films of controlled thickness; <ref type="bibr">35</ref> horizontally aligned 2D PtSe 2 layers are grown by the CVD selenization of thin Pt (typically &lt;1 nm), while vertically aligned 2D layers are achieved with thick Pt (typically &gt;4 nm). In this work, we have deliberately grown vertically aligned 2D PtSe 2 layers only as they present strong metallic transports suitable for Schottky junction formation&#57557;details are to be confirmed in the next section. Figure <ref type="figure">2a</ref>,b shows lowmagnification and high-resolution scanning TEM (HR-STEM) images of vertically aligned 2D PtSe 2 layers, respectively. The HR-STEM image in Figure <ref type="figure">2b</ref> reveals that vertically aligned 2D PtSe 2 layers expose their 2D layer edges on the surface consistent with previous studies, <ref type="bibr">35</ref> indicating the good morphological controllability of our CVD process. Figure <ref type="figure">2c</ref> shows the Raman spectra of vertically aligned 2D PtSe 2 layers exhibiting two characteristic peaks corresponding to inplane E g and out-of-plane A 1g vibration modes. <ref type="bibr">25</ref> It is noted that vertically aligned 2D PtSe 2 layers exhibit E g and A 1g peaks of comparable intensity, indicating a significant enhancement of out-of-plane vibration, similarly observed with vertically aligned 2D MoS 2 layers. <ref type="bibr">27</ref> Figure <ref type="figure">2d</ref> shows a cross-sectional STEM image of vertically aligned 2D PtSe 2 layers on a growth substrate, indicating that they are &#8764;30 nm thick. Figure <ref type="figure">2e</ref> shows the corresponding energy-dispersive X-ray spectroscopy (EDS) elemental mapping images, revealing the spatial distribution of Pt, Se, and Si. Having carried out the structural and chemical analyses of vertically aligned 2D PtSe 2 layers, we then investigated their electrical properties to assess their suitability for Schottky junction formation. We fabricated fieldeffect transistors (FETs) employing 2D PtSe 2 layers as active channels and identified their carrier transport types by characterizing FET back-gate responses, as illustrated in Figure <ref type="figure">2f</ref>. Figure <ref type="figure">2g</ref>,h shows the FET transfer characteristics of drainsource current vs. voltage (I ds -V ds ) with varying gate voltage (V g ) and I ds as a function of V g (I ds -V g ) with varying V ds obtained from vertically aligned 2D PtSe 2 layers, respectively. We note that the vertically aligned 2D PtSe 2 layers do not exhibit any FET gate responses, indicating they are highly metallic; i.e., transfer characteristics of I ds -V ds completely overlap irrespective of V g (Figure <ref type="figure">2g</ref>) and I ds does not change as a function of V g (Figure <ref type="figure">2h</ref>), consistent with our previous studies. <ref type="bibr">35</ref> Figure <ref type="figure">3</ref> presents the electrical characterization results of 2D PtSe 2 /Si Schottky junction devices. Figure <ref type="figure">3a</ref> shows the twoterminal current-voltage (I-V) characteristics of a 2D PtSe 2 / Si Schottky junction device measured with Au contacts, as shown in Figure <ref type="figure">1a</ref>. The device exhibits asymmetric rectifying  I-V characteristics with a high rectification ratio of &gt;10 3 as manifested in the corresponding semilog plot in the inset. Moreover, from the linear tangential (red slope) to the semilog plot belonging to a forward bias regime, a diode ideality factor, n, can be extracted and it is found to be &#8764;1.9. Details for the ideality factor extraction are presented in the next section. The deviation of n from unity indicates that the device performance is presently impaired by recombination of majority carriers, which is most likely attributed to unoptimized device process conditions. To confirm that the observed current rectification indeed reflects Schottky junction characteristics, we separately characterized the I-V characteristics of only-2D PtSe 2 layers and only-Si wafers without 2D PtSe 2 /Si junctions. Figure <ref type="figure">3b</ref> reveals that both 2D PtSe 2 layers and Si wafers exhibit highly symmetric Ohmic transport characteristic with Au contacts, which decisively confirms that the observed rectification originates from the 2D PtSe 2 /Si junction. To better understand the underlying transport mechanism of 2D PtSe 2 /Si Schottky junction devices, we employed temperature-variant I-V measurements. Figure <ref type="figure">3c</ref> presents the variation of I-V characteristics under varying temperature, revealing an increase of current in the forward bias regime with increasing temperature. Figure <ref type="figure">3d</ref> shows the semilog plots of the corresponding I-V characteristics with varying temperature. In addition to the increase of current in the forward bias regime, it is observed that there is a significant increase (&gt;50 times) of current in the reverse bias regime as temperature increases from 320 to 380 K. Such a temperature-dependent increase of current indicates the thermal excitation of electrons within semiconducting Si, reflecting an increase of carrier concentration in its conduction band.. <ref type="bibr">37,</ref><ref type="bibr">38</ref> From these temperature-dependent I-V plots, we further extract important material parameters, which define the performances of the Schottky junction devices; i.e., Schottky barrier height, &#934; B , and ideality factor, n. According to thermionic emission theory, <ref type="bibr">39</ref> the current, I, through a Schottky diode is expressed as</p><p>Here, I o is the reverse saturation current, which can be modeled as</p><p>Here, q is the charge of an electron, A** is the Richardson constant for Si, A is the active diode surface area, T is the absolute temperature, k is the Boltzmann constant, R s is the series resistance, and V is the voltage applied across the diode. Moreover, the diode equation can be re-expressed as 40</p><p>where J = I/A, Then</p><p>Figure <ref type="figure">3e</ref> presents the variation of &#934; B and n as a function of temperature extracted from the above equation, revealing that &#934; B increases with increasing temperature. The observation is consistent with previous studies on similarly structured 2D/3D Schottky junction devices such as graphene/Si, <ref type="bibr">41</ref> indicating that current density is dominated by thermal excitation rather than &#934; B . Meanwhile, n decreases with increasing temperature, indicating diminished carrier recombination possibly due to the thermal annihilation of structural defects at 2D PtSe 2 /Si interfaces. Moreover, the room-temperature series resistance was determined to be &#8764;529 &#937; extracted from eq 3, which is consistent with previous studies. <ref type="bibr">25,</ref><ref type="bibr">42</ref> We investigated the photovoltaic properties of 2D PtSe 2 /Si Schottky junction devices by measuring their photoresponsiveness. Figure <ref type="figure">4a</ref> demonstrates the current density-voltage (J- V) characteristics of a 2D PtSe 2 /Si junction device in dark (red) and under illumination (blue). Upon illumination with a 400 W/m 2 illumination source, the device exhibits a significant photovoltaic effect as manifested by a generation of reverse current density. Figure <ref type="figure">4b</ref> shows the semilog plot of the corresponding J-V characteristics better demonstrating photovoltaic device parameters, i.e., open-circuit voltage V oc and short-circuit current density J sc . By analyzing both Figure <ref type="figure">4a</ref>,b, we extract V oc &#8764; 0.35 V, fill factor (FF) of &#8764;26%, and J sc &#8764; 4 mA/cm 2 , which leads to a power conversion efficiency (PCE) of &#8764;1%. Figure <ref type="figure">4c</ref> describes a diagram of the energy band bending formed at the 2D PtSe 2 /Si Schottky junction, which justifies that the generation of photoexcited carriers is responsible for the observed photovoltaic effect under zero bias. The band-bending diagram is constructed based on the room-temperature &#934; B , and the electron affinity (&#967;) and band gap (E g ) of Si known from the literature. <ref type="bibr">43</ref> E c and E v are the conduction band edge and the valence band edge of Si, respectively. We note that the operational principle of 2D PtSe 2 /Si Schottky junction photovoltaics is, in principle, similar to those of other metallic 2D layers/Si-based systems. The most extensively studied one is graphene/Si heterojunction devices whose initial PCE were &#8764;1.5% in 2010, <ref type="bibr">33</ref> comparable to that 2D PtSe 2 /Si. Since then, significant efforts have been made to further improve the PCE of graphene/Si devices by engineering their intrinsic electronic/ physical structures; these efforts include adjusting band offsets and heterojunction interfaces, as well as incorporating lighttrapping structures. <ref type="bibr">44</ref> P-type doping of graphene can increase FF by reducing its sheet resistance, as well as increasing its work function (thus, Schottky barrier), as previously reported. <ref type="bibr">32,</ref><ref type="bibr">45</ref> Additionally, light-trapping materials and passivation layers have been incorporated to reduce light reflection from Si surface, as well as to improve graphene/Si interfacial morphology, respectively. <ref type="bibr">46,</ref><ref type="bibr">47</ref> The highest PCE of graphene/Si Schottky junction photovoltaics is now up to 16.2%, <ref type="bibr">48</ref> reflecting a drastic improvement over the last several years. Considering the similarity of their operational principle, we project that the photovoltaic performances of 2D PtSe 2 /Si Schottky junction devices can also be significantly improved by employing those engineering schemes developed for graphene/ Si systems. The fabrication of photovoltaic Schottky junctions via a direct growth of metallic 2D PtSe 2 layers on Si can be further extended to realize 2D PtSe 2 /Si flexible photovoltaic devices. 2D PtSe 2 layers were directly grown on thin Si wafers (thickness &lt;50 &#956;m), which were prepared by potassium hydroxide (KOH) etch followed by the device fabrication procedure described in Figure <ref type="figure">1b</ref>. Details for the KOH etching of Si are presented in the Method section. Figure <ref type="figure">4d</ref> shows a camera image of a 2D PtSe 2 /Si flexible device under mechanical bending, as well as its device components described in the inset. Figure <ref type="figure">4e</ref> presents the I-V characteristics of the same device without bending in dark (red) and under illumination (blue), as well as the corresponding semilog plot in the inset. The device exhibits a significant photovoltaic effect with V oc &#8764; 0.28 V, I sc &#8764; 0.282 mA/cm 2 , and FF &#8764; 28.75%.</p><p>We further evaluated the photovoltaic performances of 2D PtSe 2 /Si photovoltaic devices under mechanical deformation. A flexible 2D PtSe 2 /Si photovoltaic device was tested under a systematic application of controlled bending; it first underwent 100 bending cycles at a bending radius of R1 = 9.43 mm and subsequently underwent another 100 bending cycles at a bending radius of R2 = 5.95 mm (Figure <ref type="figure">5a-f</ref>). Characteristics of current density vs. voltage (J-V) were obtained after 0th, 10th, and 100th bending cycles at each radius. Figure <ref type="figure">5a</ref> shows an image of the device at a bending radius, R1. Figure <ref type="figure">5b</ref>,c represents J-V curves obtained before and after the first 100 bending cycles at R1, respectively, revealing good retention of significant photovoltaic effects. Figure <ref type="figure">5d</ref> shows an image of the same device at a bending radius, R2, after the bending shown in Figure <ref type="figure">5b,</ref><ref type="figure">c</ref>. Figure <ref type="figure">5e</ref>,f represents J-V curves obtained before and after the first 100 bending cycles at R2, respectively. We extract J sc and V oc for each bending radius and present them as a function of bending cycles in Figure <ref type="figure">5g</ref>,h, respectively. We note that V oc remains nearly constant, while J sc slightly decreases with increasing bending cycles possibly due to a pronounced generation of charge recombination sites within 2D PtSe 2 layers. The measurements were carried out under an AM 1.5 solar spectral irradiance with an intensity of 245 W/m 2 .</p><p>Finally, we provide a table to overview previous studies on 2D PtSe 2 layer-based heterojunctions, emphasizing novel aspects of this study. Table <ref type="table">1</ref> summarizes recent progresses in the development of 2D PtSe 2 layer-based heterojunction materials and devices, as well as their associated fabrication approaches. The table highlights that studies on 2D PtSe 2 /Si Schottky junction for flexible photovoltaics have not been previously explored.</p></div>
<div xmlns="http://www.tei-c.org/ns/1.0"><head>&#9632; CONCLUSIONS</head><p>In summary, we have directly grown 2D PtSe 2 layers of controlled morphological orientation and carrier transport on Si wafers and fabricated 2D PtSe 2 /Si heterojunction devices. With vertically aligned 2D PtSe 2 layers of metallic transports interfaced with Si, we have identified pronounced Schottky junction characteristics such as high-current rectification ratio, temperature-dependent barrier height, and diode ideality factors. Such intrinsic Schottky junction characteristics lead to significant photovoltaic effects upon light illumination, suggesting a technological versatility and promise of these 2D/3D electronic junctions.</p></div>
<div xmlns="http://www.tei-c.org/ns/1.0"><head>&#9632; METHOD</head><p>Flexible 2D PtSe 2 /Si Device Fabrication. Si wafers (initial thickness of &#8764;180 &#956;m) were submerged into a 30% wt KOH solution at 90 &#176;C until their thickness reached down to &#8764;20 &#956;m, following the established KOH-etching recipe. <ref type="bibr">49</ref> The remaining fabrication procedures including SiO 2 deposition and 2D PtSe 2 layer growth were carried out as instructed in Figure <ref type="figure">1b</ref>.</p><p>TEM and Raman Characterization. Microstructure analysis of 2D PtSe 2 layers was performed with a JEOL ARM 200 F Cs-corrected TEM at an operation voltage of 200 kV. For plane-view TEM sample preparation, BOE was directly applied to 2D PtSe 2 layer-grown SiO 2 /Si wafers, and the delaminated 2D PtSe 2 layers were directly onto copper TEM grids by mechanical scooping. For Raman spectroscopy characterization, a Renishaw RM 1000B system with a laser source of 514 nm wavelength was used.</p><p>Room-Temperature Electrical and Photovoltaic Characterizations. All electrical measurements were performed with a home-built probe station using a HP 4156 A semiconductor parameter analyzer. Photovoltaic measurements were carried out using an AM 1.5 G solar simulator (G2V optics) under 400 W/m 2 intensity. For the bending cyclic tests, flexible 2D PtSe 2 /Si photovoltaic devices were laminated onto self-sealing polyethylene terephthalate sheets (25 &#956;m thickness). Conductive copper tapes were attached to the front/back contacts of the devices for electrical measurements.</p><p>Variant Temperature Electrical Measurement. For temperature-dependent electrical measurements, devices were probed under vacuum inside a Janis research ST-500-UHT micromanipulated probe station, and the temperature was varied with a Lakeshore 336 cryogenic temperature controller. Electrical measurements were carried out with a Keysight B1500A semiconductor device analyzer.  </p></div>
<div xmlns="http://www.tei-c.org/ns/1.0"><head>&#9632; AUTHOR INFORMATION</head></div><note xmlns="http://www.tei-c.org/ns/1.0" place="foot" xml:id="foot_0"><p>ACS Appl. Mater. Interfaces 2019, 11, 27251-27258 Downloaded via UNIV OF CENTRAL FLORIDA on July 29, 2020 at 00:29:10 (UTC).See https://pubs.acs.org/sharingguidelines for options on how to legitimately share published articles.</p></note>
			<note xmlns="http://www.tei-c.org/ns/1.0" place="foot" xml:id="foot_1"><p>ACS Appl. Mater. Interfaces 2019, 11, 27251-27258</p></note>
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