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Title: Sensitivity Analysis of Locked Circuits
Globalization of integrated circuits manufacturing has led to increased security concerns, notably theft of intellectual property. In response, logic locking techniques have been developed for protecting designs, but many of these techniques have been shown to be vulnerable to SAT-based attacks. In this paper, we explore the use of Boolean sensitivity to analyze these locked circuits. We show that in typical circuits there is an inverse relationship between input width and sensitivity. We then demonstrate the utility of this relationship for de-obfuscating circuits locked with a class of “provably secure” logic locking techniques. We conclude with an example of how to resist this attack, although the resistance is shown to be highly circuit dependent.  more » « less
Award ID(s):
2006363
NSF-PAR ID:
10188344
Author(s) / Creator(s):
; ;
Date Published:
Journal Name:
EPiC Series in Computing
Volume:
73
ISSN:
2398-7340
Page Range / eLocation ID:
483 to 467
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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