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Title: Voltage Imaging with a NIR-Absorbing Phosphine Oxide Rhodamine Voltage Reporter
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Award ID(s):
Publication Date:
Journal Name:
Journal of the American Chemical Society
Page Range or eLocation-ID:
2304 to 2314
Sponsoring Org:
National Science Foundation
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  1. This paper presents a voltage multiplier topology that is suitable for a low-ripple high-voltage dc generation. The topology has a number of voltage multipliers connected in series and driven at different phases. Compared to a single-phase multiplier, an n-phase voltage multiplier has an output ripple that is smaller by n times. Since the ripple frequency is simultaneously increased by n times, a simple RC lowpass filter further reduces the ripple amplitude by n times, resulting in ripple reduction of n^2 times. We demonstrate the ripple reduction of the proposed topology using a 6 V-to-800 V power supply with a 16-stage four-phase bipolar voltage multiplier. The output ripple frequency is eight times the converter's switching frequency and the ripple amplitude is significantly smaller than the conventional single-phase voltage multiplier.
  2. Emerging embedded systems, such as autonomous robots/vehicles, demand a new system-on-a-chip (SoC) that is ultra-low power (mW or even sub-mW level) but highly robust. Such an SoC typically integrates heterogeneous building blocks for supporting a range of features, each ideally operating in an independent voltage and frequency (V/F) domain [1]. In such an architecture, a network-on-chip (NoC) has played a key role to enable high-speed and energy-efficient networking. However, it is increasingly challenging to meet a robustness target since each V/F domain uses a significantly different voltage, e.g., from nominal 1V to near-threshold voltage (NTV), and clock frequency, e.g., from hundreds of MHz to sub-MHz. Furthermore, any two clocks may have uncertain and time-varying phase and frequency relationships. These properties significantly worsen robustness, particularly metastability, in an NoC.