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1. Low-Ripple High-Voltage DC Generation Using a Serially Segmented Multiphase Voltage Multiplier

   https://doi.org/10.1109/ECCE44975.2020.9235707  

   Park, Sanghyeon ; Rivas-Davila, Juan ( October 2020 , 2020 IEEE Energy Conversion Congress and Exposition (ECCE))

   This paper presents a voltage multiplier topology that is suitable for a low-ripple high-voltage dc generation. The topology has a number of voltage multipliers connected in series and driven at different phases. Compared to a single-phase multiplier, an n-phase voltage multiplier has an output ripple that is smaller by n times. Since the ripple frequency is simultaneously increased by n times, a simple RC lowpass filter further reduces the ripple amplitude by n times, resulting in ripple reduction of n^2 times. We demonstrate the ripple reduction of the proposed topology using a 6 V-to-800 V power supply with a 16-stage four-phase bipolar voltage multiplier. The output ripple frequency is eight times the converter's switching frequency and the ripple amplitude is significantly smaller than the conventional single-phase voltage multiplier.
2. 25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip

   https://doi.org/10.1109/ISSCC19947.2020.9063126  

   Lin, Chuxiong ; He, Weifeng ; Sun, Yanan ; Pei, Bingxi ; Mao, Zhigang ; Seok, Mingoo ( February 2020 , IEEE International Solid-State Circuits Conference (ISSCC))

   Emerging embedded systems, such as autonomous robots/vehicles, demand a new system-on-a-chip (SoC) that is ultra-low power (mW or even sub-mW level) but highly robust. Such an SoC typically integrates heterogeneous building blocks for supporting a range of features, each ideally operating in an independent voltage and frequency (V/F) domain [1]. In such an architecture, a network-on-chip (NoC) has played a key role to enable high-speed and energy-efficient networking. However, it is increasingly challenging to meet a robustness target since each V/F domain uses a significantly different voltage, e.g., from nominal 1V to near-threshold voltage (NTV), and clock frequency, e.g., from hundreds of MHz to sub-MHz. Furthermore, any two clocks may have uncertain and time-varying phase and frequency relationships. These properties significantly worsen robustness, particularly metastability, in an NoC.
3. Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs

   https://doi.org/10.1109/MICRO.2018.00039  

   Zou, An ; Leng, Jingwen ; He, Xin ; Zu, Yazhou ; Gill, Christopher D. ; Janapa Reddi, Vijay ; Zhang, Xuan ( October 2018 , IEEE/ACM International Symposium on Microarchitecture (MICRO))
4. Clock-Voltage Co-Regulator With Adaptive Power Budget Tracking for Robust Near-Threshold-Voltage Sequential Logic Circuits

   https://doi.org/10.1109/TCSI.2019.2948944  

   Nguyen, Bai ; Tang, Nghia ; Hong, Wookpyo ; Zhou, Zhiyuan ; Heo, Deukhyoun ( February 2020 , IEEE Transactions on Circuits and Systems I: Regular Papers)
5. An Active Zero-State Switch (AZS) for Commonmode Voltage Reduction in Voltage Source Inverter (VSI) Drives

   https://doi.org/10.1109/APEC39645.2020.9124003  

   Zhang, Zhe ; Bazzi, Ali M. ; Semin, Afia ( March 2020 , IEEE Applied Power Electronics Conference)