In this paper, we propose a new dynamic reliability technique
using an accuracy-reconfigurable stochastic computing (ARSC) framework
for deep learning computing. Unlike the conventional stochastic computing
that conducts design time accuracy power/energy trade-off, the new ARSC
design can adjust the bit-width of the data in run time.
Hence, the ARSC can mitigate the long-term aging effects by slowing
the system clock frequency, while maintaining the inference throughput by
reducing the data bit-width at a small cost of accuracy. We show how to
implement the recently proposed counter-based SC multiplication and
bit-width reduction on a layer-wise quantization scheme for CNN networks
with dynamic fixed-point data. We validate an ARSC-based five-layer
convolutional neural network designs for the MNIST dataset based on Vivado
HLS with constraints from Xilinx Zynq-7000 family xc7z045 platform.
Experimental results show that new ARSC DNN can sufficiently compensate
the NBTI induced aging effects in 10 years with marginal classification
accuracy loss while maintaining or even exceeding the pre-aging computing
throughput. At the same time, the proposed ARSC
computing framework also reduces the active power consumption due to the
frequency scaling, which can further improve system reliability due to the
reduced temperature.
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Run-time accuracy reconfigurable stochastic computing for dynamic reliability and power management: work-in-progress
In this paper, we propose a novel accuracy-reconfigurable stochastic
computing (ARSC) framework for dynamic reliability and power
management. Different than the existing stochastic computing works,
where the accuracy versus power/energy trade-off is carried out in
the design time, the new ARSC design can change accuracy or
bit-width of the data in the run-time so that it can accommodate the
long-term aging effects by slowing the system clock frequency at
the cost of accuracy while maintaining the throughput of the
computing. We validate the ARSC concept on a discrete cosine
transformation (DCT) and inverse DCT designs for image
compressing/decompressing applications, which are implemented on
Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the
long-term aging-induced effects by accuracy trade-off while
maintaining the throughput of the whole computing process using simple
frequency scaling. We further show that one-bit precision loss for the
input data, which translated to 3.44dB of the accuracy loss in term
of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently
compensate the NBTI induced aging effects in 10 years while maintaining
the pre-aging computing throughput of 7.19 frames per second. At the same
time, we can save 74\% power consumption by 10.67dB of accuracy loss.
The proposed ARSC computing
framework also allows much aggressive frequency scaling, which can lead to
order of magnitude power savings compared to the traditional dynamic
voltage and frequency scaling (DVFS) techniques.
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- NSF-PAR ID:
- 10279539
- Date Published:
- Journal Name:
- Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’20), ESWEEK 2020
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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