Stochastic computing (SC) is a re-emerging computing paradigm providing low-cost and noise-tolerant designs for a wide range of arithmetic operations. SC circuits operate on uniform bit-streams with the value determined by the probability of observing 1’s in the bit-stream. The accuracy of SC operations highly depends on the correlation between input bit-streams.
While some operations such as minimum and maximum value functions require highly correlated inputs, some other such as multiplication operation need uncorrelated or independent inputs for accurate computation. Developing low-cost and accurate correlation manipulation circuits is an important research in SC as these circuits can manage correlation between bit-streams without expensive bit-stream regeneration. This work proposes a novel in-stream correlator and decorrelator circuit that manages 1) correlation between stochastic bit-streams, and 2) distribution of 1’s in the output bit-streams. Compared to state-of-the-art solutions, our designs achieve lower hardware cost and higher accuracy. The output bit-streams enjoy a low-discrepancy distribution of bits which leads to higher quality of results. The effectiveness of the proposed circuits is shown with two case
studies: SC design of sorting and median filtering
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High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing
Multiply-accumulate (MAC) operations are common
in data processing and machine learning but costly in terms
of hardware usage. Stochastic Computing (SC) is a promising
approach for low-cost hardware design of complex arithmetic
operations such as multiplication. Computing with deterministic
unary bit-streams (defined as bit-streams with all 1s grouped
together at the beginning or end of a bit-stream) has been recently
suggested to improve the accuracy of SC. Conventionally, SC
designs use multiplexer (MUX) units or OR gates to accumulate
data in the stochastic domain. MUX-based addition suffers
from scaling of data and OR-based addition from inaccuracy.
This work proposes a novel technique for MAC operation
on unary bit-streamsthat allows exact, non-scaled addition of
multiplication results. By introducing a relative delay between
the products, we control correlation between bit-streams and
eliminate OR-based addition error. We evaluate the accuracy of
the proposed technique compared to the state-of-the-art MAC
designs. After quantization, the proposed technique demonstrates
at least 37% and up to 100% decrease of the mean absolute
error for uniformly distributed random input values, compared
to traditional OR-based MAC designs. Further, we demonstrate
that the proposed technique is practical and evaluate area, power
and energy of three possible implementations.
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- Award ID(s):
- 2019511
- NSF-PAR ID:
- 10281280
- Date Published:
- Journal Name:
- IEEE Transactions on Computers
- Volume:
- 71
- ISSN:
- 0018-9340
- Page Range / eLocation ID:
- 1 to 1
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1109/TC.2021.3087027
