skip to main content


Title: Engineering the interface chemistry for scandium electron contacts in WSe 2 transistors and diodes
Abstract

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS2, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe2transistors with impressive subthreshold slope (109 mV dec−1) andION/IOFF(106) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe2in situbefore metallization, which minimizes subsequent reactions between Sc and WSe2. Post metallization anneals in reducing environments (UHV, forming gas) degrade theION/IOFFby ~103and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe2, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe2layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe2Fermi level around individual Sc atoms in the WSe2lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe2transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe2.

 
more » « less
NSF-PAR ID:
10308395
Author(s) / Creator(s):
; ; ; ; ; ; ; ; ; ; ; ;
Publisher / Repository:
IOP Publishing
Date Published:
Journal Name:
2D Materials
Volume:
6
Issue:
4
ISSN:
2053-1583
Page Range / eLocation ID:
Article No. 045020
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. Abstract

    This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe2) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe2SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

     
    more » « less
  2. Abstract

    New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.

     
    more » « less
  3. Abstract

    Molybdenum oxide thin films are successfully deposited using spatial atomic layer deposition (SALD), a tool designed for high‐throughput industrial film growth. The structural and optical properties of the film are evaluated using ultraviolet photoelectron spectroscopy, high‐resolution transmission electron microscopy, and spectroscopic ellipsometry. To demonstrate the applicability of molybdenum oxide in industrial settings the films are applied as hole‐selective silicon heterojunction contacts for solar cells. When paired with intrinsic amorphous silicon passivation layers, implied open‐circuit voltages of 699 mV are achieved. The carrier transport is unaffected by low‐temperature contact anneals up to 300 °C with contact resistivities of ≈ 10 mΩ cm2. Finally, the optical performance of silicon solar cells featuring different front hole‐selective heterojunction structures are simulated. It is shown that the generation current density of heterojunction solar cells can be significantly increased with the addition of SALD molybdenum oxide contacts.

     
    more » « less
  4. The study investigates the mitigation of radiation damage on p‐type SnO thin‐film transistors (TFTs) with a fast, room‐temperature annealing process. Atomic layer deposition is utilized to fabricate bottom‐gate TFTs of high‐quality p‐type SnO layers. After 2.8 MeV Au4+irradiation at a fluence level of 5.2 × 1012 ions cm−2, the output drain current and on/off current ratio (Ion/Ioff) decrease by more than one order of magnitude, field‐effect mobility (μFE) reduces more than four times, and subthreshold swing (SS) increases more than four times along with a negative shift in threshold voltage. The observed degradation is attributed to increased surface roughness and defect density, as confirmed by scanning electron microscopy (SEM), high‐resolution micro‐Raman, and transmission electron microscopy (TEM) with geometric phase analysis (GPA). A technique is demonstrated to recover the device performance at room temperature and in less than a minute, using the electron wind force (EWF) obtained from low‐duty‐cycle high‐density pulsed current. At a pulsed current density of 4.0 × 105 A cm−2, approximately four times increase inIon/Ioffis observed, 41% increase inμFE, and 20% decrease in the SS of the irradiated TFTs, suggesting effectiveness of the new annealing technique.

     
    more » « less
  5. Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (T≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InOx). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InOx) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (Rc< 160 Ω cm) and competitive transistor performance (µlinup to 19 cm2V−1s−1, Subthreshold Slope (SS) ≤150 mV dec−1) with only low‐temperature processing (T≤ 250 °C).

     
    more » « less