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  • Monolithic 3D semiconductor footprint scaling exploration based on VFET standard cell layout methodology, design flow, and EDA platform
Title: Monolithic 3D semiconductor footprint scaling exploration based on VFET standard cell layout methodology, design flow, and EDA platform
Award ID(s):
2110419
PAR ID:
10342988
Author(s) / Creator(s):
; ; ;
Editor(s):
Moaiyeri, Mohammad Hossein
Date Published:
Journal Name:
IEEE access
ISSN:
2169-3536
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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