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This content will become publicly available on January 17, 2024

Title: High-Level Approaches to Hardware Security: A Tutorial
Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits or take advantage of “backdoors” in a design. Unintended design bugs can also result in security weaknesses. This tutorial paper provides an introduction to the domain of hardware security through two pedagogical examples of hardware security problems. The first is a walk-through of the scan chain-based side channel attack. The second is a walk-through of logic locking of digital designs. The tutorial material is accompanied by open access digital resources that are linked in this article.
Authors:
; ;
Award ID(s):
2039607
Publication Date:
NSF-PAR ID:
10391979
Journal Name:
ACM Transactions on Embedded Computing Systems
ISSN:
1539-9087
Sponsoring Org:
National Science Foundation
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