Chen, Chixiao, Yin, Jieming, Peng, Yarui, Palesi, Maurizio, Cao, Wenxu, Huang, Letian, Singh, Amit Kumar, Zhi, Haocong, and Wang, Xiaohang. Design Challenges of Intrachiplet and Interchiplet Interconnection. Retrieved from https://par.nsf.gov/biblio/10417489. IEEE Design & Test 39.6 Web. doi:10.1109/MDAT.2022.3203005.

Chen, Chixiao, Yin, Jieming, Peng, Yarui, Palesi, Maurizio, Cao, Wenxu, Huang, Letian, Singh, Amit Kumar, Zhi, Haocong, & Wang, Xiaohang. Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Design & Test, 39 (6). Retrieved from https://par.nsf.gov/biblio/10417489. https://doi.org/10.1109/MDAT.2022.3203005

Chen, Chixiao, Yin, Jieming, Peng, Yarui, Palesi, Maurizio, Cao, Wenxu, Huang, Letian, Singh, Amit Kumar, Zhi, Haocong, and Wang, Xiaohang. "Design Challenges of Intrachiplet and Interchiplet Interconnection". IEEE Design & Test 39 (6). Country unknown/Code not available. https://doi.org/10.1109/MDAT.2022.3203005. https://par.nsf.gov/biblio/10417489.

@article{osti_10417489,
place = {Country unknown/Code not available}, title = {Design Challenges of Intrachiplet and Interchiplet Interconnection}, url = {https://par.nsf.gov/biblio/10417489}, DOI = {10.1109/MDAT.2022.3203005}, abstractNote = {}, journal = {IEEE Design & Test}, volume = {39}, number = {6}, author = {Chen, Chixiao and Yin, Jieming and Peng, Yarui and Palesi, Maurizio and Cao, Wenxu and Huang, Letian and Singh, Amit Kumar and Zhi, Haocong and Wang, Xiaohang}, }