Yasin, Atif, Su, Tiankai, Pillement, Sebastien, and Ciesielski, Maciej. Formal Verification of Divider Circuits by Hardware Reduction. Retrieved from https://par.nsf.gov/biblio/10439133. 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2023) . Web. doi:10.1109/SMACD58065.2023.10192137.

Yasin, Atif, Su, Tiankai, Pillement, Sebastien, & Ciesielski, Maciej. Formal Verification of Divider Circuits by Hardware Reduction. 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2023), (). Retrieved from https://par.nsf.gov/biblio/10439133. https://doi.org/10.1109/SMACD58065.2023.10192137

Yasin, Atif, Su, Tiankai, Pillement, Sebastien, and Ciesielski, Maciej. "Formal Verification of Divider Circuits by Hardware Reduction". 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2023) (). Country unknown/Code not available. https://doi.org/10.1109/SMACD58065.2023.10192137. https://par.nsf.gov/biblio/10439133.

@article{osti_10439133,
place = {Country unknown/Code not available}, title = {Formal Verification of Divider Circuits by Hardware Reduction}, url = {https://par.nsf.gov/biblio/10439133}, DOI = {10.1109/SMACD58065.2023.10192137}, abstractNote = {}, journal = {2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD-2023)}, author = {Yasin, Atif and Su, Tiankai and Pillement, Sebastien and Ciesielski, Maciej}, }