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Connecting two surface-code patches may require significantly higher noise at the interface. We show, via circuit-level simulations under a depolarizing noise model with idle errors, that surface codes remain fault tolerant despite substantially elevated interface error rates. Specifically, we compare three strategies—direct noisy links, gate teleportation, and a CAT-state gadget—for both rotated and unrotated surface codes, and demonstrate that careful design can mitigate hook errors in each case so that the full code distance is preserved for both 𝑋 and 𝑍. Although these methods differ in space and time overhead and performance, each offers a viable route to modular surface-code architectures. Our results, obtained with stim and pymatching, confirm that high-noise interfaces can be integrated fault-tolerantly without compromising the code's essential properties, indicating that fault-tolerant scaling of error-corrected modular devices is within reach with current technology.
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Performance and power modeling and prediction using MuMMI and 10 machine learning methods
Summary Energy‐efficient scientific applications require insight into how high performance computing system features impact the applications' power and performance. This insight can result from the development of performance and power models. In this article, we use the modeling and prediction tool MuMMI (Multiple Metrics Modeling Infrastructure) and 10 machine learning methods to model and predict performance and power consumption and compare their prediction error rates. We use an algorithm‐based fault‐tolerant linear algebra code and a multilevel checkpointing fault‐tolerant heat distribution code to conduct our modeling and prediction study on the Cray XC40 Theta and IBM BG/Q Mira at Argonne National Laboratory and the Intel Haswell cluster Shepard at Sandia National Laboratories. Our experimental results show that the prediction error rates in performance and power using MuMMI are less than 10% for most cases. By utilizing the models for runtime, node power, CPU power, and memory power, we identify the most significant performance counters for potential application optimizations, and we predict theoretical outcomes of the optimizations. Based on two collected datasets, we analyze and compare the prediction accuracy in performance and power consumption using MuMMI and 10 machine learning methods.
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- PAR ID:
- 10443320
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- Concurrency and Computation: Practice and Experience
- Volume:
- 35
- Issue:
- 15
- ISSN:
- 1532-0626
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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