allium nitride (GaN) power devices have been commercialized up to 900 V. Vertical GaN devices are under extensive development for kilovolt applications [1]. Edge termination is an essential building block of any vertical power device to laterally spread the crowded electric field (E-field) at the electrode edge and enable high breakdown voltage (BV).
Several edge termination designs, including field plate [2], [3], deep or bevel mesa [4]- [9], isolation implant [10], guard ring [11]- [13], junction termination extension (JTE) [14]- [19], and their combinations, have been demonstrated in vertical GaN p-n diodes. Among these designs, JTE is of great interest as it has become the mainstream choice in industrial Si and SiC devices [20]. State-of-the-art JTEs are featured by a decreased charge density away from the active region, which allows for higher efficiency and broader design space as compared to the single-zone (non-graded) JTE [20]- [22].
The fabrication of GaN JTEs is more challenging than SiC and Si, due to difficulties in p-type implantation or diffusion. Current GaN JTE fabrication mostly relies on the compensation implant into an epitaxial p-GaN to form a single-zone JTE [14], [16], which suffers from small process windows (e.g., requiring precise control of the implant depth down to 10 nm [16]). On the other hand, the graded charge profile has only been enabled by the beveled etch [5], [9] instead of implantation in GaN.
In addition to high BV, edge termination is also the key to enabling avalanche capability, which allows devices to pass a high avalanche current (I AVA ) at BV. While a vital signature of avalanche is a positive temperature coefficient of BV, the robust avalanche for passing the high I AVA has to be tested by inductive switching circuits [23]. Among various GaN terminations, such a robust avalanche has only been reported in a single-zone JTE [19] and two bevel-etched terminations [6], [9].
This work demonstrates a novel, etch-free, single-implant GaN JTE that has a graded charge profile and enables the circuit-level avalanche. A new process is developed to produce a tapered dielectric layer with an ultra-small bevel angle, which serves as the mask for nitrogen implantation to compensate the p-GaN. The produced bevel JTE is embedded in bulk GaN and far from the surface. Therefore, its effectiveness is insensitive to the interface charge commonly introduced by the passivation. An on-wafer avalanche circuit test is performed, and the key physics is unveiled by physics-based TCAD simulation.
Fig. 1(a) shows the 3D schematic of the proposed JTE, the ultra-small-angle bevel JTE (USAB-JTE). The uncompensated p-GaN at the device edge exhibits a wedge shape with a large ratio between the JTE width (W) and thickness (T). The wafer comprises 20 nm p ++ -GaN ([Mg]: 10 20 cm -3 ), 500 nm p-GaN ([Mg]: 10 19 cm -3 ) and 10 μm n-GaN ([Si]: 10 16 cm -3 ), grown by Enkris Semiconductor Inc. on a 2-inch GaN substrate from Nanowin Co., Ltd. The net donor concentration (N D -N A ) in n-GaN is 8×10 15 cm -3 as revealed from C-V measurements.
TCAD simulations based on the models in [17] are used to quantify the impact of the bevel angle on the peak E-field. Fig. 1(c) shows the simulated E-field profile along the junction for the JTEs with various W/T ratios. A higher ratio allows the peak E-field to be more effectively suppressed. This trend agrees with the simulation results in [24] for a bevel-etched GaN JTE. As compared to the prior tapered PR formed by the greyscale lithography [21] and reflow technique [5], [9], our Al 2 O 3 mask shows a smoother surface, smaller angle, and superior hardness for implantation. At the edge of the p-GaN active region, the Al 2 O 3 thickness is 190 nm (Fig. 2(c)).
This tapered Al 2 O 3 is then used as the mask for nitrogen (N) implantation. The implantation design aims at a full and partial p-GaN compensation in the un-masked and masked region, respectively. Here a five-energy implantation with energies of 25, 80, 150, 240, and 320 keV and doses of 8.54, 1.51, 1.36, 5.81, and 4.48×10 12 cm -2 is used to produce a box-like profile. Monte Carlo simulations [25] confirms a compensation depth (N defect density higher than [Mg]) of 400 nm and 610 nm with the 190 nm Al 2 O 3 mask and without mask, respectively. In this way, the small bevel angle in the Al 2 O 3 mask is transferred to the un-compensated p-GaN, forming a USAB-JTE with T of ~120 nm and W of ~75 µm (Fig. 2(c)).
Before this implantation, a PR is coated on top of the anode region for protection. Finally, anode and cathode are formed. A control device with only the through p-GaN implant isolation is also fabricated. The radius of the anode metal and p-GaN active region is 100 µm and 110 µm, respectively, for all diodes described in this paper.
We finally discuss the manufacturability and tunability of the above dielectric mask process. The Al 2 O 3 thickness (480 nm) is redundant to show a large process window. An Al 2 O 3 slightly thicker than the inner edge of the mask (190 nm) is sufficient. Also, the deposition rate can be much higher using by plasmaenhanced chemical vapor deposition (PECVD) [26], further allowing for reductions in the deposition and etch time.
A wide range of dielectric bevel angles can be produced by tuning the lateral or vertical etch rate. The former can be raised by lowering the PMGI baking temperature. The bevel angle is found to be 0.09 o to 0.03 o for baking at 200 o C and 160 o C, respectively. The vertical etch rate can be adjusted by varying the TMAH concentration or dielectric materials. For example, the TMAH etch rate of PECVD SiO 2 and SiN x is 0.07~0.45 nm/min [27] and 0.08~1.3 nm/min [28], respectively. both devices are non-destructive and repeatable as well as possess a positive temperature coefficient (η T ), suggesting the dominant role of the impact ionization (I. I.) in the breakdown. Note that a positive η T may not ensure the robust avalanche to pass high I AVA , as the avalanche could occur locally or be intervened by trap-filling [17].
Unclamped inductive switching (UIS) circuit test is a routine method to validate the high I AVA avalanche capability of power devices. In the UIS test, device is first ON to charge the inductor. Device is then turned-OFF, and the inductive energy is dissipated in the device through avalanching. The working principle and circuit design are detailed in [19]. Here we develop an on-wafer UIS test platform, which directly connects the UIS board to the probe station (Fig. 4(a)-(b)) to enable the test of the as-fabricated devices without the need for packaging.
Fig. 4(c) show the voltage and current waveforms of the diodes with and without the USAB-JTE in the UIS tests with an increased device-ON time (t ON ) and inductive energy. The JTE diodes show classic avalanche waveforms with the voltage clamped at the avalanche BV and the current reduced to zero. At 1.7 kV, the I AVA is higher than 1100 A/cm 2 . In contrast, the diode without JTE shows a destructive failure at the capacitive charging phase. This failure behavior is identical to that of the non-avalanche device under the UIS test [29], suggesting the diodes without JTE have no capability to dissipate a high I AVA .
TCAD simulations are performed using the Selberherr I. I. model with the experimental I. I. coefficients in [30]. Fig. 5(a) and (b) show the simulated contours of the I. I. generation rate and E-field in the JTE diodes with an acceptor concentration (N A ) of 6×10 18 cm -3 , considering a doping efficiency (N A /[Mg]) of 60~70% reported in p-GaN due to the M-H complexes that cannot be fully broken in the annealing [31]. As shown, while the peak E-field is at the JTE outer edge, the peak I. I. location moves to the active device region. This guides the I AVA to flow through the active region, allowing for a high I AVA . Table I benchmarks the key metrics (robustness, fabrication, efficiency) of the avalanche-capable edge terminations reported in vertical GaN devices. Here the efficiency is defined as the ratio between the device BV AVA and the parallel-plane BV AVA limit (𝐵𝑉 𝑃𝑃 𝐴𝑉𝐴 ). 𝐵𝑉 𝑃𝑃 𝐴𝑉𝐴 is calculated from the punch-through E- )) [32] fitted by the I. I. coefficients in [30]. The comparison shows that our USAB-JTE simultaneously achieves the circuit-level avalanche, simple etch-free fabrication, and high efficiency in vertical GaN.
We demonstrate an etch-free, single-implant USAB-JTE that enables the circuit-level avalanche in vertical GaN devices. This JTE relies on a new fabrication process to form a USAB, tapered dielectric mask for implantation. This process has wide material and device applicability. The USAB-JTE shows good potential as a building block for a variety of high-voltage, avalanche-robust vertical GaN devices. [9] Yes Yes 1 0 0.835 86% Single-zone JTE [14] No No 0 1 2.4 e) 87% a) UIS circuit tests; b) I-V characteristics showing a positive temperature coefficient of BV; c) detailed implant design not disclosed; d) highest BV with positive temperature coefficient reported in [3]; e) avalanche claimed based on light emission during the I-V sweep.