From its inception, extensive work on the characterization of field effect transistors (FETs) based on 2D‐layered semiconductors has relied on a back‐gated transistor architecture. This is useful for initial assessment but lacks ultimate compatibility with integrated circuit (IC) design since the threshold voltage of individual devices cannot be controlled independently in order to achieve specific ON‐state and OFF‐state performance. Note that threshold engineering via gate electrostatics is inevitable for 2D semiconductors owing to the absence of comprehensive, reliable, and universal doping schemes. In recent years, several strategies are adopted for the gating of individual 2D‐FETs such as atomic layer deposition (ALD) of high‐
The interconnect half‐pitch size will reach ≈20 nm in the coming sub‐5 nm technology node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be >4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross‐section and they are much more resistive than Cu, the effective conductance of an ultrascaled interconnect will be compromised by the thick bilayer. Therefore, 2D layered materials have been explored as diffusion barrier alternatives. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back‐end‐of‐line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. Here, a 2D layered tantalum sulfide (TaS
- NSF-PAR ID:
- 10460503
- Publisher / Repository:
- Wiley Blackwell (John Wiley & Sons)
- Date Published:
- Journal Name:
- Advanced Materials
- Volume:
- 31
- Issue:
- 30
- ISSN:
- 0935-9648
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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