With trend in technology scaling down and the data rate increasing continuously, high-speed channel design and optimization have become more challenging [1]. Maintaining signal integrity is an inevitable challenge for high-speed printed circuit board (PCB) designers during the product development stage [2]. In high-speed channels, vertical interconnects, commonly known as vias, are used to route signals on different layers for different channels, which are typical impedance discontinuity inducing components in high-speed channels, which can result in profound signal integrity and power integrity issues. Thus, it is essential to design the vias with high electrical performance, to meet required impedance, return loss, and insertion loss specifications.
Generally, 3D full-wave simulation software, such as HFSS and CST, are used for the optimization of the via transition. Based on 3D full-wave simulation, the via stub resonance, the impact of non-functional pads and the ground via numbers were investigated in [3]. The time domain impedance (TDR) for the through hole vias, the blind vias and the buried vias was studied in [4]. Due to the structural complexity of the via transition and high number of design parameters for optimization, the via optimization by 3D fullwave simulation is very time consuming. Many equivalent models for high-speed differential via pair have been developed to reduce the optimization time. A differential via pair modeling methodology was introduced in [5], where accuracy decreases after 20 GHz. Moreover, some modeling strategies of the highspeed via was investigated in paper [6] and non-function pads placement optimization for high-speed channel based on multiple reflection theory was proposed [7], [8]. However, to apply techniques introduced in [7] and [8], accurate high-speed differential via model is required.
To help reduce the high-speed channel design time, this paper introduces the high-speed differential via optimization based on a physics-based via model with high accuracy and high bandwidth, which can work up to 70 GHz, for the first time. The proposed physics-based equivalent model of differential via verified by 3D full-wave simulation (ANSYS HFSS). Unlike the conventional physics-based via models, the proposed equivalent circuit model considers the impact of the higher-order modes in the parallel-plate for increased accuracy in high frequency region. In addition, the change in electrical performance with respect to change in the anti-pad radius, the via pitch and the ground (GND)-via-to-differential-via distance are analyzed. The electrical performance of differential via pair can be accurately and rapidly optimized based on the proposed model, to save time during high-speed channel design.
A high-accuracy and high-bandwidth single signal via model was proposed in [9]. The application range of the highaccuracy and high-bandwidth via model was investigated in [10]. Based on the high-accuracy and high-bandwidth equivalent circuit model of single signal via, the physics-based equivalent circuit model of the differential via pair with the individual anti-pad is proposed in this paper, as shown in Figure 1, which corresponds to differential via pair segment crossing a cavity enclosed by two reference plates. The equivalent circuit model includes four capacitors for the via-to-parallel-plate coupling, the high-order mode parallel-plate impedances ′ for each signal via, and the 4 by 4 Z matrix for the coupling of all vias due to fundamental parallel-plate mode. In the 4 by 4 Z matrix, the self-impedance Zii represents the fundamental parallel-plate impedance for each via while the mutualimpedance Zij represents the via coupling due to the fundamental parallel-plate mode. The key difference with the previous method [6] is that the proposed equivalent model considers the impact of higher-order parallel-plate modes, to achieve high accuracy for high bandwidth application.
The coupling capacitance between the via and the parallel plate has been analyzed in the past, and the via-to-plate capacitance calculations are proposed in [11], [12], and [13]. In this paper, the coupling capacitances are calculated based on [12].
The self-impedance represents the coupling between the via and the parallel-plate due to the fundamental parallel-plate mode, which can be calculated in terms of the modal fields. When the parallel plate is infinitely large or the boundary condition of the plate consists of perfectly matched layers (PMLs), the self-impedance can be calculated as [14] (1)
, where is the via number, is the radius of the via. ′′, which is a complex wavenumber. !" # # and !" # # $%&'( ) * + ,/2 , and is the angular frequency. # and " are the permittivity and permeability of free space, respectively. # is relative permittivity, %&'( is the loss tangent of the dielectric material, / 0 !2/ " 1 is the skin depth of conductor with conductivity of 1. h and t are the parallel-plate height and plate thickness, respectively. 2 and 2 3 is the zero-order and first-order Hankel function of the second kind, relatively. When the parallel plate is finite or the boundary condition of the plate is a perfect electric or magnetic conductor (PEC or PMC) boundary, the self-impedance can be calculated based on the cavity method [15].
The mutual-impedance represents the coupling between the vias due to the fundamental parallel-plate mode, which can also be calculated by the modal fields. When the parallel plate is infinitely large, we can calculate the mutual-impedance as [14] 4 5 6 $ 5 , 4 (6) Where is the via number, is the radius of the via, is the pitch size of the via and of the via. 7 is the zeroorder Bessel function. When the parallel plate is finite, the mutual impedance can be calculated based on the cavity method [15]. The high-order parallel-plate modes impedances ′ for each signal via can also be calculated in terms of the modal fields, which are excited at the anti-pad boundary. For the higher- order modes, only TM0n modes are considered here. Because the via structure we consider is circular and symmetric, only TM0n modes (higher-order modes, which are axially isotropic modes) are excited [16]. The impedance ′ is calculated as
where = ! $'>/ℎ, , n represents the mode number, N is the total number of higher-order modes it counts for the via modeling. The derivation of can be found in the reference [9].
In this section, the proposed equivalent circuit model of differential via pair with adjacent GND vias is verified 3D fullwave numerical simulation. Change in electrical performance due additional high-order parallel plate modes is analyzed. Based on the proposed model, the differential via pair's electrical performance can be optimized by parametric analysis on the via pitch, the anti-pad radius and GND-via-todifferential-via distance.
Figure 2 shows the top view and the side view of the differential via pair with GND vias with 6 GND layers, for 3D full-wave numerical simulation. All via radius are while the anti-pad radius is 4 , the parallel-plate high is ℎ and each plate thickness is %. The signal via pitch is 00 and the via pitch for the signal via and the GND via is 0@ . The boundary condition for the model is PML.
In first set of analysis, the and 4 are 5 mils and 10 mils, respectively. Meanwhile, the ℎ and the % are 10 mils and 1 mil, the 00 and 0@ are both 40 mils. The total thickness of the model is 56 mils. The comparison between the differential insertion loss and the differential return loss of the differential via model are plotted in Figure 3, between the proposed equivalent model and HFSS results. The red solid curve are the results from the 3D full-wave numerical simulation, ANSYS HFSS, the black dotted curve are the results from the proposed equivalent model while the blue dotted curve represents the results from the conventional physics-based equivalent model from [6].
We can observe that the differential S-parameters from the proposed equivalent model shows high correlation with the 3D full-wave numerical simulation, up to 100 GHz. However, the differential S-parameters from the conventional physics-based equivalent model shows much larger difference with the simulation results above 40 GHz because it does not consider the high-order parallel-plate modes impedance ' . The proposed equivalent model's high accuracy at high frequency is verified. . In addition, the importance of high-order parallelplate modes for high frequency via modeling is also verified..
To investigate the effect of changes in anti-pad radius, the anti-pad radius is swept from 10 mils to 20 mils with a step of 5 mils in the second case. All other geometrical parameters of the differential via are unchanged from the first case in sub-section A. The differential S-parameters of the differential via are plotted in Figure 4.
The differential insertion loss from the proposed model shows high level of correlation with the simulation results up to 70 GHz. The differences in differential insertion loss between the proposed model and the simulation is less than 2 dB. The differential return loss from the proposed model also shows relatively a high level of correlation with simulation results, with the exception of a few frequency points where the magnitude is below -30 dB.
Additionally, the differential insertion loss decreases with the increase of the anti-pad radius. The differential return loss can be decreased below 30 GHz and can be increased above 40 GHz with the increase of the anti-pad radius.
The proposed model accurately model the effect of change in anti-pad radius on electrical performance.
The effect of change in via pitch on the differential via's electrical performance is analyzed in the third case. The 00 is equal to the 0@ . They are both swept from 30 mils to 50 mils with a step of 10 mils. The anti-pad radius for the signal via is 30 mils. Except the anti-radius and the via pitch size, other geometrical parameters of the differential via remain unchanged as the configurations in the first case. The differential Sparameter comparison of the differential via is plotted in Figure 5.
From the differential S-parameter comparison, it is verified again that the proposed model can accurately model the differential via up to 70 GHz, both for differential insertion loss and the differential return loss. Differential insertion loss and the differential return loss of the differential via can decrease for a larger via pitch above 30 GHz. However, for the frequencies below 20 GHz, the larger via pitch can result in increased the differential return loss.
For fourth set of analysis, the signal via pitch 00 is fixed as 40 mils, but the pitch 0@ of signal via and the GND via is swept from 20 mils to 40 mils, with 10 mils step. Similarly, the geometry configurations of the differential via remains unchanged as the differential via in third set of analysis. The differential S-parameters are plotted in Figure 6.
The proposed model continues to show high correlation to simulation. The distance 0@ between the signal via and the GND via can also affect the differential via's electrical performance. Unlike the third set of analysis, the small GNDvia-to-differential-via distance can help decrease the differential insertion loss and the differential return loss in the frequencies above 30 GHz because the return current return loop size for the differential via pair decreases as the GND-via-to-differential-via distance decreases.
The proposed equivalent model of the differential via pair with adjacent GND vias is verified up to 70 GHz. The effects of the anti-pad radius, the via pitch and GND-via-to-differential-via distance are analyzed. In addition, the computational resource cost of the first set of analysis in 3D full-wave FEM simulation and the proposed model are compared in table I. The simulation was conducted in a server with 3.45 GHz CPU and 512 GB RAM memory. The proposed method is shows higher time and resource efficiency when compared to 3D full-wave simulation with comparable level of accuracy. PCB designers can use the proposed model to optimize high speed channels with at reduced computational resources and time.
High-accuracy and high-bandwidth physics-based equivalent circuit model of differential via pair with the individual anti-pad and adjacent GND vias is proposed in the paper, for the first time. The accuracy of the proposed equivalent circuit model is verified using comparison to 3D full-wave numerical simulation over multiple cases studies with different anti-pad radius, via pitch size and GND-via-todifferential-via distance up to 70 GHz. Differential via can be optimized by increasing the anti-pad radius or decreasing the via pitch size. Decreasing the GND-via-to-differential-via distance can also help improve the differential via's electrical performance. When compared to 3D full-wave numerical simulation, the proposed model can save computational resources and time. The proposed differential via model will allow high speed channel designers to optimize differential via with different parameters with reduced computation resources and time. Most importantly, the proposed model also provides physical insight to guide differential via optimization for highspeed channels.
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