A Build-in Gate Driver Design for 1.7kV SiC MOSFET Module with 32-chip Paralleled

L. Du, Y. Chen

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A Build-in Gate Driver Design for 1.7kV SiC MOSFET Module with 32-chip Paralleled

Award ID(s):: 1939144

PAR ID:: 10492917

Author(s) / Creator(s):: L. Du, Y. Chen

Publisher / Repository:: ," 2023 IEEE Applied Power Electronics Conference and Exposition

Date Published:: 2023-05-01

Format(s):: Medium: X

Sponsoring Org:: National Science Foundation

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