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1. Scalable Concolic Testing of RTL Models

   https://doi.org/10.1109/TC.2020.2997644  

   Lyu, Yangdi; Mishra, Prabhat (January 2020, IEEE Transactions on Computers)

   Simulation is widely used for validation of Register-Transfer-Level (RTL) models. While simulating with millions of random or constrained-random tests can cover majority of the functional scenarios, the number of remaining scenarios can still be huge (hundreds or thousands) in case of today's industrial designs. Hard-to-activate branches are one of the major contributors for such remaining/untested scenarios. While directed test generation techniques using formal methods are promising in activating branches, it is infeasible to apply them on large designs due to state space explosion. In this paper, we propose a fully automated and scalable approach to cover the hard-to-activate branches using concolic testing of RTL models. While application of concolic testing on hardware designs has shown some promising results in improving the overall coverage, they are not designed to activate specific targets such as uncovered corner cases and rare scenarios. This paper makes two important contributions. (1) We propose a directed test generation technique to activate a target by effective utilization of concolic testing on RTL models. (2) We develop efficient learning and clustering techniques to minimize the overlapping searches across targets to drastically reduce the overall test generation effort. 

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2. Simulator Independent Coverage for RTL Hardware Languages

   https://doi.org/10.1145/3582016.3582019  

   Laeufer, Kevin; Iyer, Vighnesh; Biancolin, David; Bachrach, Jonathan; Nikolić, Borivoje; Sen, Koushik (March 2023, ACM)
3. Simulator Independent Coverage for RTL Hardware Languages

   Kevin Laeufer, Vighnesh Iyer (January 2023, 28th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'23))
4. Automated Generation of Security Assertions for RTL Models

   https://doi.org/10.1145/3565801  

   Witharana, Hasini; Jayasena, Aruna; Whigham, Andrew; Mishra, Prabhat (January 2023, ACM Journal on Emerging Technologies in Computing Systems)

   System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is widely used for functional validation of Register-Transfer Level (RTL) designs. Assertions can improve the controllability and observability that can lead to faster error detection and localization. Although assertions are widely used for functional validation of RTL models, there is limited effort in applying assertions to detect SoC security vulnerabilities. Specifically, a fundamental challenge in SoC security and trust validation is how to develop high-quality security assertions. In this article, we perform automated vulnerability analysis of RTL models to generate security assertions for six classes of vulnerabilities. Experimental results show that the generated security assertions can detect a wide variety of vulnerabilities. Our automated framework can drastically reduce the overall security validation effort compared to the manual development of security assertions. Automated generation of security assertions will enable assertion-based verification to be one of the most promising pre-silicon security sign-off solutions. 

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5. RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement

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   Arias, Orlando; Liu, Zhaoxiang; Guo, Xiaolong; Jin, Yier; Wang, Shuo (March 2022, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE))