Nag, Shashank, Susskind, Zachary, Arora, Aman, Bacellar, Alan_T_L, Dutra, Diego_L_C, Miranda, Igor_D_S, Kailas, Krishnan, John, Eugene_B, Breternitz, Mauricio, Lima, Priscila_M_V, Franca, Felipe_M_G, and John, Lizy_K. LogicNets vs. ULEEN : Comparing two novel high throughput edge ML inference techniques on FPGA. Retrieved from https://par.nsf.gov/biblio/10539985.

Nag, Shashank, Susskind, Zachary, Arora, Aman, Bacellar, Alan_T_L, Dutra, Diego_L_C, Miranda, Igor_D_S, Kailas, Krishnan, John, Eugene_B, Breternitz, Mauricio, Lima, Priscila_M_V, Franca, Felipe_M_G, & John, Lizy_K. LogicNets vs. ULEEN : Comparing two novel high throughput edge ML inference techniques on FPGA. Retrieved from https://par.nsf.gov/biblio/10539985.

Nag, Shashank, Susskind, Zachary, Arora, Aman, Bacellar, Alan_T_L, Dutra, Diego_L_C, Miranda, Igor_D_S, Kailas, Krishnan, John, Eugene_B, Breternitz, Mauricio, Lima, Priscila_M_V, Franca, Felipe_M_G, and John, Lizy_K. "LogicNets vs. ULEEN : Comparing two novel high throughput edge ML inference techniques on FPGA". Country unknown/Code not available: IEEE Digital Library. https://par.nsf.gov/biblio/10539985.

@article{osti_10539985,
place = {Country unknown/Code not available}, title = {LogicNets vs. ULEEN : Comparing two novel high throughput edge ML inference techniques on FPGA}, url = {https://par.nsf.gov/biblio/10539985}, abstractNote = {}, journal = {}, publisher = {IEEE Digital Library}, author = {Nag, Shashank and Susskind, Zachary and Arora, Aman and Bacellar, Alan_T_L and Dutra, Diego_L_C and Miranda, Igor_D_S and Kailas, Krishnan and John, Eugene_B and Breternitz, Mauricio and Lima, Priscila_M_V and Franca, Felipe_M_G and John, Lizy_K}, }