Introduction

Organic semiconductors (OSCs) have attracted significant interest due to their chemical versatility and unique properties, offering mechanical flexibility, lightweight and cost-effective processing. These attributes make them promising candidates for a range of applications, including organic light-emitting diodes (OLEDs), flexible and wearable electronics, sensors, organic photovoltaics (OPVs), and organic field-effect transistors (OFETs). [1][2][3][4][5] OFETs serve as a platform for investigating the mechanism of charge transport in OSCs, and represent the fundamental building blocks of organic electronic circuits. [6][7][8] Over time, advancements in material and device design have resulted in remarkable performance, and charge carrier mobilities exceeding 10 cm 2 V À1 s À1 have been reported in both small molecules and polymer OFETs. [9][10][11][12][13][14][15] However, to establish the applicability of OFETs in real-world applications, it is important to also address their stability when subjected to various stress factors, including electrical, mechanical, chemical, environmental, and thermal stress. While significant progress has been made in enhancing the stability of p-type OFETs, and threshold voltage shifts smaller than 0.2 V have been demonstrated even under aggressive bias stress in ambient conditions, 16 the development of n-channel devices has comparatively lagged behind. Nevertheless, the field is rapidly advancing, with more n-type OFETs with mobilities exceeding 1 cm 2 V À1 s À1 becoming available, and research into their stability increasingly gaining momentum. [13][14][15][17][18][19][20][21] Among the most investigated acceptor building blocks are diimides functionalized acceptors, 19,[22][23][24][25][26][27][28][29] diketopyrrolopyrrole (DPP), [30][31][32][33][34] isoindigo (IID), 35 benzodifurandione-based oligo(p-phenylene vinylene) (BDOPV), 20,[36][37][38][39][40] showcasing significant progress in optimizing charge transport and environmental stability. [41][42][43][44] Improving operational stability is equally important, as prolonged bias stress usually leads to instabilities that can significantly impact performance. 16,45,46 Device degradation typically manifests as a decrease in charge carrier mobility and drain current, a shift in threshold voltage, and/or an increase in the subthreshold slope and off-current. 41 Such changes in the current-voltage (I-V) characteristics hold significant implications for the performance of electronic and optoelectronic applications based on these OFETs. Addressing bias-stress degradation in n-channel OFETs is extremely challenging due to the susceptibility of the semiconductor layer to oxidation, which is further exacerbated under the application of an electric field. This vulnerability arises from the relatively high energy of its lowest unoccupied molecular orbital (LUMO), typically exceeding À4 eV, which makes it prone to reduction by common degradation agents. The processing conditions, the semiconductor film composition and morphology, and device geometry have been shown to impact both the environmental and the bias stress stability of n-channel thin-film transistors based on both small molecule and conjugated polymers (CPs). 21,[47][48][49][50][51][52][53] A threshold voltage shift of 2.9 V has been achieved under moderate bias stress, establishing a benchmark for further advancements in operational stability. 49 The current performance gap between n-type and p-type OFETs, particularly in terms of operational stability, poses a significant challenge to the development of high-performance, low-cost integrated circuits (ICs). Achieving a balanced performance between n-type and p-type OFETs is crucial for expanding the design space of organic integrated circuits and accelerating their adoption in mainstream applications. Herein, we strategically engineered the device architecture and the chemical structure of the organic semiconductor to achieve high performance n-channel OFETs with exceptional bias-stress stability. The semiconductor layers consisted of donor-acceptor polymers based on Indacenodithiazole (IDTz) ladder-type core and a DPP acceptor unit flanked via a thiophene donor linker. We optimized polymer configurations through varying the alkylation on their backbone (branched vs. linear chains). By chemically tailoring the electrodes with self-assembled monolayers (SAMs), we tuned the device channel from p-to n-type and achieved a remarkable electron mobility of 1.3 cm 2 V À1 s À1 in the most optimized devices. Notably, our n-type OFETs demonstrated exceptional operational stability, as evidenced by the negligible change in mobility and remarkably low threshold voltage shift of DV th = 0.5 V attained under prolonged continuous bias stress under high electric fields, which persisted for over 1000 min testing in a vacuum atmosphere.

Results and discussion

The chemical structures of the IDTz-DPP polymers P1-P3 are illustrated in Fig. 1a. The DPP core has several appealing properties, including excellent stability, strong electron deficiency, great aggregation, flexibility to accommodate long alkyl side chains and good thermal stability. 54 In our design, we selected a five-membered heterocycle, i.e. thiophene, as a flanking aromatic unit, which minimizes steric stress onto the DPP core and promotes a highly planar polymer backbone, a critical factor for achieving high charge carrier mobilities. 55 The IDTz monomer is the analogue to the widely employed ladder donor unit, indacenodithiophene (IDT), which has been extensively used to create high-performance CPs for various applications, including OFETs. 9,[56][57][58] In the case of IDTz, a more electron-deficient thiazole unit replaces the thiophene unit found in IDT and this substitution leads to a deeper LUMO. [59][60][61] Sidechain engineering of conjugated polymers represents a powerful tool for tuning their semiconducting properties. [62][63][64] The sidechains not only enhance the solubility, but also play a crucial role in film morphology, p-p stacking, and electronic communications thereby influencing the transport of charge carriers. 55,65,66 In this study, the polymers share a common backbone but differ in their alkyl substituent patterns, providing test platforms to investigate how the alkylation pattern impacts the effectiveness and stability of charge transport.

In Fig. 1b we show the UV-vis absorption spectra of P1, P2 and P3 in chloroform solutions, along with the spectra of the freshly cast films and of films annealed at 110 1C and 270 1C.

In solution, all copolymers show similar features: a p-p* transition around 430 nm and two distinct peaks at 670 nm and 730 nm, corresponding to 0-1 and 0-0 transitions, respectively. In thin films, these peaks redshift and the 670 nm band intensifies, indicating interchain p-p stacking. Lowtemperature (110 1C) annealing further enhances the 670 nm band and 430 nm absorption, with P2 showing a fourfold increase in the 430 nm absorption, possibly due to the formation of a new conductive band. Annealing at 270 1C amplifies this band, which becomes dominant in all polymers, while the 670/730 nm bands nearly vanish for P2 and are reduced for P1 and P3. The evolution of the absorption spectra with annealing emphasizes the role of alkyl side chains in the structural re-organization of the films during thermal treatment.

The charge transport properties and bias stress stability have been evaluated using top-gate, bottom-contact OFETs, 6 the device architecture is shown in Fig. 2a. To create n-type devices, the source/drain contacts have been modified with polyethyleneimine ethoxylated (PEIE), 67 while pentafluorobenzenethiol (PFBT) was used for p-channel OFETs. 68,69 The dielectric consisted of a bilayer of Cytop and parylene C subsequently deposited. 16 Device transfer characteristics were measured by sweeping the V GS while keeping the V DS fixed at À60 V (for hole transport, left panel Fig. 2b) and 60 V (for electron transport, left panel Fig. 2c). The corresponding output curves for OFETs based on polymer P1 are depicted in the right panels of Fig. 2b and c, respectively. The charge carrier mobilities were determined to be m h = 0.3 cm 2 V À1 s À1 (for hole transport), and m e = 1.3 cm 2 V À1 s À1 (for electron transport). The I-V characteristics for the other two polymers are shown in Fig. S1 and S2 in the ESI, † along with the hysteresis data (Fig. S3, ESI †). At least 40 different OFETs of each type have been measured across multiple substrates and all devices that were considered for the analysis exhibited ideal or nearly ideal I-V characteristics. 8,70 The non-zero intersection observed in the n-type output curves is likely attributed to the high contact resistance in these devices, as we will discuss later. Although the hole mobilities are relatively modest, the measured electron mobilities are on par with the best reported. 22,23,30,31,35,36 To assess the impact of annealing temperature on charge carrier mobility, we fabricated four sets of samples for each polymer, maintaining a consistent device architecture, while varying the annealing temperatures. The maximum annealing temperature was chosen based on thermogravimetric analysis (TGA, Fig. S4, ESI †) and differential scanning calorimetry (DSC, Fig. S5, ESI †) to maximize performance without compromising material integrity. The dependence of device mobility on annealing temperature is presented in Fig. S6, ESI. † Based on this analysis, we have established optimal annealing protocol for each polymer.

Results for 110 1C and the annealing temperature yielding the highest performance are presented in Fig. S7, ESI † and Table 1, demonstrating a clear enhancement in mobility upon annealing across all samples. Such response to thermal annealing is consistent with the results obtained on other polymers and was assigned to improved morphology of the semiconductor film, leading to reduced charge carrier trapping and lower contact resistance. [71][72][73] P1 displayed the highest mobility under both Table 1 Comparative study on all three polymers for performance and bias stress stability. Here, LTA = low temperature annealing (110 1C) and HTA = high temperature annealing (280-310 1C)

m 0 LTA P1 0.4 0.3 AE 0.04 1.2 0.9 P2 0.1 0.05 AE 0.01 1.6 0.8 P3 0.2 0.1 AE 0.02 0.5 1.1 HTA P1 1.3 1 AE 0.2 2.6 0.90 P2 0.8 0.6 AE 0.1 1.9 1.02 P3 0.5 0.4 AE 0.1 1.5 1

low and high-temperature annealing conditions. The threefold improvement in mobility in films annealed at elevated temperatures suggests that the organization of alkyl groups plays a crucial role in establishing a favorable material morphology. Conversely, P2, which features exclusively straight dodecyl groups, exhibited an impressive eightfold improvement after high-temperature annealing. We hypothesize that while linear alkyl groups cannot yield an optimal configuration at moderate annealing temperatures, they can accommodate the alignment necessary for high performance when heated sufficiently. Polymer P3 demonstrated the smallest increase in mobility and the lowest final performance despite having the highest mass of the set. This observation may indicate that the presence of alkyl chains on both monomeric cores introduces excess entropic freedom, potentially disrupting electronic communication within the film. It also underscores the importance of reducing entropic freedom to optimize performance upon annealing. 74,75 While the molecular structure of the polymer influences charge transport within the OFET channel, the efficiency of charge injection at the electrode-semiconductor interface is a critical factor determining mobility values (Table 1). Injectionlimited transport often manifests as a dependence of mobility on device geometry; however, our data (Fig. S8 and S9, ESI †) reveals no clear trend. The work function of the Au electrode modified with PEIE (3.9 eV) lies significantly below the LUMO levels of all three polymers (P1 : 3.51 eV, P2 : 3.38 eV, P3 : 3.37 eV, see Fig. S10, ESI †), suggesting the formation of a Schottky barrier at the interface. The height of this barrier influences charge injection efficiency and, consequently, the overall device mobility. To further investigate the relationship between charge injection and mobility, we conducted contact resistance analysis on our OFET devices using the gated Transmission Line Model (Fig. S11, ESI †). 6,76 The results reveal a subtle correlation between contact resistance and mobility, with P1, the polymer with the highest mobility, exhibiting the lowest contact resistance. This suggests that while the molecular structure of P1 contributes to its superior charge transport properties, the lower contact resistance plays an important role.

To understand the impact of film morphology on the electrical properties, we investigated the microstructure of the thin films using grazing-incidence wide-angle X-ray scattering (GIWAXS) measurements. Fig. 3 includes the 2D patterns images acquired on the films that have been annealed at recorded for a near amorphous n-type polymer being m e = 0.34 cm 2 V À1 s À1 . 78 The results presented so far certify the high-performance of our n-type polymer OFETs, with mobilities exceeding 1 cm 2 V À1 s À1 . Considering the limited prior work on the bias stress stability of such devices, our subsequent investigations will focus exclusively on the n-type devices. We conducted operational stability tests on all n-type OFETs. During these measurements, the transistors were kept under continuous operation (V GS = V DS = 60 V) for over 1000 min, with short interruptions at regular intervals to measure the transfer characteristics. Fig. 4a shows the evolution of the transfer characteristics measured in devices based on polymer P1 annealed at low temperatures, the results obtained on polymer P1 upon high temperature annealing, as well as on polymers P2 and P3 are included in Fig. S14-S16 (ESI †), while in Fig. S17 (ESI †) we plot the evolution of the drain and subthreshold slope under bias stress. The changes recorded in the I-V curves are extremely small, in spite of the fact that these OFETs have been subjected to an aggressive bias stress protocol. To inspect these changes more carefully and quantitatively assess the device instabilities, we plotted the evolution of threshold voltage and charge carrier mobility as a function of bias stress time; the results are shown in Fig. 4b. These graphs correspond to average values obtained upon measuring multiple OFETs annealed at low temperature and the corresponding data obtained upon high temperature annealing is included in Fig. S18 (ESI †). Notably, the threshold voltage shift DV th is exceptionally low in all devices (DV th o 1.6 V), with values of DV th = 0.5 V being recorded in OFETs based on P3. Furthermore, the changes in mobilities are minimal. Several interesting observations from these results warrant further discussions. Firstly, the highest temperature needed during post-processing was 110 1C, making this technology compatible with flexible substrates. P3 exhibits the lowest charge carrier mobility, but the highest stability, suggesting that the optimal chemical structure of the polymer may differ when it comes to controlling these two properties. Secondly, it appears that the post-processing treatment for high mobility diverges from those yielding the highest stability. As such, the LTA devices were the most stable under bias stress degradation, despite having lower mobility compared to HTA films. While these conclusions are based on a limited data set, they provide the foundation for a more systematic and ample future study aimed at the development of polymer semiconductors that excel in both performance and stability.

The formation of electronic traps has been recognized as being the main reason for performance degradation in organic devices. 16 To monitor the evolution of trap density during the operational stability tests, we analyzed the density of trap states (trap-DOS) using the Gru ¨nwald method. 16,[81][82][83][84] Fig. 5a shows the trap DOS plotted as a function of energy E relative to the conduction band E C for each device type, and the two curves correspond to the trap-DOS spectrum before (black) and after (color) the application of bias stress for 1000 min. These graphs confirm the fact that the bias stress instabilities are a direct consequence of the generation of charge carrier traps upon bias stress. In Fig. 5b we include the schematic representation of the energetic and spatial distribution of trap states in the band gap of an organic semiconductor functioning in an n-channel OFET. Tail states near the band edges give rise to shallow, acceptor-like traps and deep trap states located within the band gap form a distinct peak. The peak is not apparent in our experimental results given the limited energy range accessible to us from transistor measurements. To quantitatively determine the density of the trap states created during bias stress, the difference between the two curves was evaluated for each polymer (yellow highlight). The density of traps increased by 2.6 Â 10 15 states per cm 3 in P1, 2.5 Â 10 15 states per cm 3 in P2, and 4.8 Â 10 14 states per cm 3 in P3. These minimal changes in all polymers are in agreement with the small shifts in V th and m recorded in all samples and are partially due to the chosen device architecture, in which the dielectric layer also encapsulates the polymer films, limiting the diffusion of water and oxygen. 16 Notably, the value of the density of traps generated in P3 is an order of magnitude lower than in P1 and P2, which explains its highest stability and suggests that the chemical composition of the polymers also plays a role in bias stress stability. While assessing the morphological evolution of the polymer films under bias stress could offer insights into the nature of trap formation (as seen in Fig. 5), our current top-gate device architecture precludes direct observation of the polymer layer post-stress. The overlying gate dielectric and electrode layers prevent access to the active material, limiting our ability to characterize any potential morphological changes induced by bias stress. Transitioning to a bottom-gate configuration would enable direct access to the polymer film, facilitating the analysis of such morphological changes. This approach could clarify the underlying mechanisms of degradation and potentially guide the development of strategies to mitigate these effects, thereby further enhancing device stability. Shelf-life stability tests have also been performed;

the results are shown in Fig. S19 in the ESI. † The trends are consistent with those obtained in operational stability tests, where P3 is notably more stable compared to P1 and P2.

Having demonstrated exceptional bias stress stability, the subsequent challenge lies in understanding the influence of mechanical strain on device performance. [85][86][87] This is of paramount importance for the advancement of flexible electronics, as maintaining robust performance on curved surfaces and ensuring reproducibility in technologically relevant thin-film configurations represent crucial steps towards realizing their full potential.

Conclusions

In summary, our study assessed the performance and stability of OFETs fabricated on donor-acceptor polymers incorporating IDTz and DPP units, alkylated with branched and/or linear side chains. Through tailored electrode surface modification, we tuned the charge transport from p to n-type, resulting in electron mobilities exceeding 1 cm 2 V À1 s À1 in devices with near-ideal current-voltage characteristics. Remarkably, these devices exhibited minimal changes in mobilities, and exceptionally low threshold voltage shifts of 0.5 V were achieved under the application of bias stress at a constant 60 V for 1000 min in vacuum. Real-time monitoring of the trap density of states revealed that the degradation is caused by the formation of electronic trap states in the polymer bandgap and their density was proportional to the threshold voltage shift.

Our findings indicate that a combination of linear and branched substituents is necessary for achieving high mobility.

On the other hand, a high density of branched sidechains contributed to better stability, but negatively impacted charge carrier mobility. This suggests that the optimal polymer chemical structure for performance and stability may not align offering initial guidance for engineering materials that withstand bias stress. While this work provides valuable insights, establishing a comprehensive relationship between polymer structure, OFET design, and bias stress stability would require examining a larger dataset. Nevertheless, this study successfully addresses several key aspects necessary for developing a robust model linking these parameters, thus opening exciting avenues for future research in tailoring stable and high-performance organic electronics. The ultimate goal is to achieve both operational and environmental robustness. This requires addressing a multitude of factors that influence OFET stability, including material properties, device architecture, and environmental conditions. Our work serves as a significant step forward by decoupling these factors with focusing on operational stability under vacuum conditions. The exceptional bias stress resilience demonstrated by our n-type polymer OFETs reveals the potential of these polymers for operational stability. Further investigations into developing effective encapsulation strategies will be crucial to ensuring consistent performance in ambient conditions. Looking ahead, the high bias-stress stability demonstrated in our n-type polymer transistors represents a crucial step towards their incorporation into complex larger-scale organic integrated circuits.

Experimental

Polymer synthesis

Starting materials were received from Sigma-Aldrich, Fisher Scientific or Alfa Aesar. Tetrakis(triphenylphosphine)palladium (Pd(PPh 3 ) 4 , 99% (99.9+%-Pd)) was used as received from Strem Chemicals. All solvents were obtained from VWR and used without any further purification unless stated otherwise. IDTz monomers were synthesized according to previously reported procedures, 60 while the DPP monomers were purchased from Solarmer. Flash chromatography on silica gel (pore size 60 Å, particle size 230-400 mesh) was used to purify the products, while Celite (Supleco R566) was used for filtration. Reactions were monitored by TLC on Merck Silica Gel 60 Å F-254 precoated plates (0.25 mm thickness), and components were visualized under 254 and 365 nm UV light. All the syntheses were performed using standard Schlenk techniques involving oven-dried glassware and Teflon coated stir bars under a dry argon atmosphere. Copolymers P1-P3 were synthesized using Stille coupling reaction. This involved reacting IDTz dibromides with stannylated DPP monomers in refluxing chlorobenzene, Pd(PPh 3 ) 4 was used as the catalyst, following the procedures described in Fig. S20, ESI. † Both monomers were used in 0.1 mmol amount with 5% mol Pd(PPh 3 ) 4 as the catalyst refluxing at 140 1C in 1 ml of dry chlorobenzene. All Stille polymerization reactions were performed using microwave type vials heated in aluminum blocks for 24 hours. The polymeric materials were precipitated into acidified methanol, then purified by soxhlet extraction for 24 hours with order of solvents: methanol, acetone, n-heptane.

Last fractions of the polymers were washed with chloroform, concentrated, precipitated in methanol, filtered, and dried under high vacuum. Number-average molecular weights (M n ) and dispersities (Ð) of all copolymers were measured via size exclusion chromatography (SEC) in chlorobenzene using polystyrene as a standard (Fig. S21-S23, ESI †). Polymer molecular weights were determined using Agilent 1260 Infinity II high temperature GPC/SEC system (Agilent Technologies) using chlorobenzene as the eluent at 80 1C. Column set was calibrated with narrow polystyrene standards. The copolymers have M n in the range of 40-65 kg mol À1 with Ð = 1.5-1.9, as summarized in Table S1

OFET fabrication and characterization

OFETs were fabricated on Si wafer substrates terminated with a 200 nm layer of thermally grown SiO 2 , diced into pieces of approximately 1.5 Â 1.5 cm 2 . Prior to device fabrication, the substrates were cleaned in an acetone bath, then an isopropanol (IPA) bath, both at 85 1C. After drying under nitrogen, the substrates were exposed to UV-ozone treatment, then rinsed with deionized water to remove any residual organic matter, and dried again under nitrogen. Next, 3/40 nm of Ti/Au were deposited onto the clean substrates through a shadow mask to define the source and the drain electrodes. Channel lengths ranged from 30 mm to 100 mm, and channel widths ranged from 200 mm to 1000 mm. Multiple chips were measured for each fabrication condition. To create n-type devices a 0.05% solution of PEIE in 2-methoxyethanol was spin-coated onto the substrates with pre-defined contacts at a spinning speed of 5000 rpm for 60 seconds, followed by a rinse with a mild flow of deionized water. The sample was dried under N 2 gas and then annealed at 110 1C for 10 min in a nitrogen environment.

To fabricate p-type OFETs, the substrates were immersed in a solution of 20 mL of PFBT in 5 mL of high-purity ethanol for 30 min to allow self-assembly onto the contacts. After the treatment, the samples were rinsed with ethanol for 30 seconds and then dried with N 2 gas. The polymers were spun-coated from a 5 mg mL À1 solution in room temperature chlorobenzene at 2000 rpm for 60 seconds. The resulting films have been annealed on a preheated hotplate for 10 min at 110 1C, 250 1C, semiconducting polymer film at 2000 rpm for 60 seconds. The stack was then annealed on a hot plate at 110 1C for 25 min under nitrogen and placed in a vacuum desiccator overnight at room temperature. Next, a 300 nm parylene-C layer was deposited onto the Cytop layer in a custom-built reactor consisting of a quartz tube maintained at low pressure (10 À2 torr) and divided into three distinct temperature zones. In the first section, the dimer di-para-xylene was heated at a temperature of 120 1C to sublime into dimeric gas, which was then passed into the second sector through a hot furnace where the temperature was maintained at 700 1C. The dimer then dissociated into its gaseous monomers inside the furnace. This resulted in monomeric gases polymerized onto the device placed in the third region of the tube maintained at room temperature forming a uniform conformal coating. The resulting bilayer dielectric has a final areal capacitance of C i = 1.28 nF cm À2 . Finally, a 40 nm layer of Au was thermally evaporated onto the device array through a shadow mask and served as a top gate electrode. Devices were electrically characterized using an Agilent 4155 Semiconductor Parameter controlled by LabVIEW and/or SweepMe! Software (sweep-me.net). All measurements were performed in the dark and under vacuum (10 À5 torr). The charge carrier mobility (m) was determined from the slope of the square root of the drain current OI D versus the gate-source voltage V GS plot in the saturation regime. 6 We ensured that the leakage current was at least two orders of magnitude lower than the drain current in all OFETs considered for analysis.

Stability tests on OFETs

Operational (bias-stress) stability tests were performed in vacuum (10 À5 torr), in the dark, at room temperature. A continuous drain-source V DS and gate-source V GS voltage was applied for at least 1000 min at high voltages of V GS = V DS = 60 V and the saturation regime transistor characteristics were acquired at 30-minute intervals. At least 3 different devices of each type have been investigated and the results were found to be consistent. For the shelf-life tests, the saturation regime transfer characteristics (I D vs. V GS at V DS = +60 V) were recorded once a week for at least 10 weeks. After each measurement, the samples were stored in a vacuum with minimum exposure to light and ambient atmosphere.

Grazing-incidence wide-angle X-ray scattering (GIWAXS) measurements

The GIWAXS experiments were carried out at ALBA Synchrotron (Barcelona, Spain), at NCD-SWEET scattering beamline. HTA and LTA polymer samples were prepared on PEIE treated silicon substrates, by using similar processing conditions as for OFET fabrication. We measured the sample in grazingincidence geometry, projecting the X-ray beam on the thin film samples at an incident angle between 0.11 and 0.21. The energy of the beam was set to 12.4 keV (l = 0.1 nm) and the size of the beam to 50 mm  50 mm. The samples were exposed to the beam for 5 seconds, and the patterns were collected with a LX255-HS (Rayonix) detector. Several frames were taken to increase the signal-to-noise ratio.