Ahmadi, Kasra, Aghapour, Saeed, Mozaffari_Kermani, Mehran, and Azarderakhsh, Reza. Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder. Retrieved from https://par.nsf.gov/biblio/10567348. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32.11 Web. doi:10.1109/TVLSI.2024.3419700.

Ahmadi, Kasra, Aghapour, Saeed, Mozaffari_Kermani, Mehran, & Azarderakhsh, Reza. Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 32 (11). Retrieved from https://par.nsf.gov/biblio/10567348. https://doi.org/10.1109/TVLSI.2024.3419700

Ahmadi, Kasra, Aghapour, Saeed, Mozaffari_Kermani, Mehran, and Azarderakhsh, Reza. "Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 (11). Country unknown/Code not available: IEEE. https://doi.org/10.1109/TVLSI.2024.3419700. https://par.nsf.gov/biblio/10567348.

@article{osti_10567348,
place = {Country unknown/Code not available}, title = {Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder}, url = {https://par.nsf.gov/biblio/10567348}, DOI = {10.1109/TVLSI.2024.3419700}, abstractNote = {}, journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, volume = {32}, number = {11}, publisher = {IEEE}, author = {Ahmadi, Kasra and Aghapour, Saeed and Mozaffari_Kermani, Mehran and Azarderakhsh, Reza}, }