Analog/Mixed-signal (AMS) integrated circuit (IC) design typically follows a process flow visualized in Figure 1. A combination of designer experience and computer simulation feedback is iterated to determine the design that meets the performance requirements. A large portion of design time is spent on the sizing and layout phases, where multiple iterations are possible due to potential loop-backs in the design flow. This is a labor-intensive process in industry practice with little to no automation. To address this costly exercise, a considerable effort in academia is focused on introducing automated solutions.
Analog sizing automation is the task of optimizing AMS design variables, e.g., transistor widths, lengths, resistor, and capacitor values. The aim is to satisfy the performance constraints and optimize the design objective. In general, sizing automation is run through schematic-level simulations. However, AMS IC performance is also sensitive to layout implementation [1]. Especially in the advanced process nodes, layout-induced parasitics may greatly affect the final design performance. Therefore, sizing the AMS design variables considering the layout effects is also crucial.
The majority of the recent sizing and post-layout performance optimization algorithms have simulation feedback in
Device sizing
Integration/Fabrication Fig. 1: AMS Design Flow the loop. Due to advanced scaling, simulations are required to obtain accurate performance evaluations. Simulation-based AMS automation algorithms adapted various methods from the optimization and Machine Learning (ML) communities. The earlier approaches include population-based methods such as particle swarm optimization [2] and evolutionary algorithms [3]. Although these algorithms have good convergence behavior, they are inefficient in sampling since they explore the design space randomly. To mitigate sample inefficiency, model-based methods gained popularity [4]- [6]. These methods employ surrogate-models between the solution space and performance space and provide efficiency in exploring the solution space. A typical surrogate model is Gaussian Process Regression (GPR) [7], which is a well-studied model in Bayesian Optimization (BO) field [8] and is adapted by several analog sizing algorithms. The main drawback of GPR modeling is its computational complexity. Recent research trend in analog sizing introduces ML to simulation-based methodology [9]. However, the literature review reveals that most of these methods require thousands of simulation data to train Deep Neural Network (DNN) models that approximate the relations between the design variables and the performance metrics. Therefore, the practicality of these algorithms is severely reduced when the optimization task has a high simulation cost. For example, drawing/generating the layout, extracting the parasitics, and running post-layout simulations is typically an expensive procedure. Therefore, optimization algorithms designed for schematic-level sizing can not be adapted by simply changing how data is generated. This paper presents a Machine Learning-based simulationin-the-loop automation method for the AMS design problem. Overall, we formalize two stand-alone recipes for schematiclevel sizing and post-layout performance optimization, i.e., layout-aware sizing. We integrate the state-of-the-art analog layout generator, MAGICAL [10], into our flow to handle layout-aware sizing. Our algorithms do not assume the preexistence of any dataset, and we generate all training data during the optimization. We employ Bayesian Neural Networks (BNN) for modeling design performances. Bayesian Neural Networks allow error quantification, and compared to Deep Neural Networks, BNN are shown to be effective in handling scarce datasets and preventing overfitting [11]. Therefore, BNN can be trained on smaller datasets, significantly improving the practicality and scalability. We also introduce a batch-optimization framework and design space sampling strategy that is compatible with BNN modeling. Further, when optimizing the design variables based on post-layout performance, we exploit the correlation between schematiclevel simulations and post-layout simulations. Our algorithm introduces a co-learning scheme that reduces the need for costly post-layout simulations and boosts efficiency even further. We compile our contributions as follows:
• We use Bayesian Neural Network-based modeling to obtain performance approximations. Different learning strategies are adapted for schematic-level sizing and postlayout performance optimization. • We adopt a scalable sampling strategy and query the optimization batches by utilizing a trust region and Thompson sampling.
• The post-layout sizing is handled as a multi-fidelity optimization problem, and an efficient co-learning strategy is developed. • The efficiency of the proposed methods is demonstrated on three circuits by providing comparisons to previous state-of-the-art.
The rest of the paper is organized as follows. Section II introduces the backgrounds and previous work. Section III describes our algorithms for handling schematic-level sizing and post-layout performance-based sizing problems. Section IV provides the experiments on circuit examples to demonstrate the efficiency of our algorithms. Finally, Section V concludes the paper.
In this section, we first formally define the AMS design automation problem. Then we review the recent approaches to schematic-level sizing and layout-aware sizing. We summarize the state-of-the-art algorithms' advantages and shortcomings.
In this paper, we assume that the existence of post-layout performance implies the existence of schematic-level performance values. However, the reverse implication does not hold.
We formulate the AMS schematic-level sizing and layoutaware sizing task as a constrained optimization problem succinctly as below.
where, x ∈ R d is the parameter vector and d is the number of design variables of sizing task. Thus, R d is the design space. f 0 (x) is the objective performance metric we aim to minimize. Without loss of generality, we denote i th constraint by f i (x).
Notice that if the problem is schematic-level optimization, the f i values are obtained from schematic simulations. If the problem is post-layout optimization, the f i values are determined by post-layout simulations.
Through this paper, we will evaluate the quality of a design by defining a Figure of Merit (FoM) in the following form:
where w i is the weighting factor. Note, a max(•) clipping is used for equating designs after constraints are met, and min(•) is used to prevent single constraint violation from dominating FoM value.
The recent methods for AMS sizing can be collected under two algorithm classes: Bayesian Optimization methods and Deep Learning methods.
Bayesian Optimization methods are tested on AMS problems and are proven to be sample efficient. For example, GASPAD [4] is a hybrid algorithm using a combination of evolutionary space exploration and GPR surrogate-based selection. WEIBO [5] method also employs GPR as a surrogate and introduces a Bayesian Optimization framework where a weighted acquisition function is tailored to comply with the performance-constrained nature of sizing problem. In [6], the authors introduced a multi-fidelity GPR algorithm where the fidelity of the performance is varied with the simulation accuracy. However, this work did not address the layout effects. The disadvantage shared by all GPR models is their cubic complexity to the number of samples, O(N 3 ).
Deep Learning based sizing methods includes supervised learning and reinforcement learning (RL) methods [12]- [16]. GCN-RL [13] is a Graph Neural Network algorithm where state representation is built via device index, type, and selected electrical properties. They also propose methods to transfer the optimization experience between different topologies and processes. However, their training graphs show that they use up to 10 4 simulations for sizing academic circuits. AutoCkt [14] is a discrete action space policy gradient method. The RL agent is trained on different optimization tasks where the task is randomly sampled from a predefined set. The trained agent is then tested for the particular tests during deployment. We also observe from the training graphs that AutoCkt requires up to 10 5 simulated samples for training. In [17], the authors successfully applied BNN on multi-objective analog sizing. Si m ul at e t h e q n e w q u er y p oi nts a n d o bt ai n s p e cs f (X t ) vi a S PI C E si ms
w h er e µ is t h e m e a n a n d σ 2 is t h e v ari a n c e a p pr o xi m ati o n. are typically computationally expensive. Therefore, methods are sought to further increase the efficiency of the (BNNbased) optimization algorithm. As a solution, we treat this problem as a multi-fidelity problem where we have access to two different information sources for calculating circuit performance metrics. Considering that the schematic-level simulations are less accurate approximations of post-layout level simulations, we define these information sources as schematic-level simulations having the lower fidelity and postlayout simulations are the highest fidelity.
We modify the BNN architecture to capture two levels of fidelities (Figure 2) at the output and propose a co-learning scheme similar to multi-task BNN learning [23]. The multifidelity BNN model has two output nodes where ϕ(x) [1] models the lower fidelity prediction, i.e., schematic-level performance prediction, and ϕ(x) [2] models the high fidelity prediction, i.e., post-layout performance prediction. Under the assumption that we have access to two levels of information sources, we denote the new dataset by D = D 1 ∪ D 2 , where
n=1 and the joint probability of the updated BNN model is given by:
where p(θ) = N (vec(θ) | 0, I) and N k is the number training points in given fidelity level k. The joint probability expression is a combination of the data sourced from both types of simulations; therefore, we utilize the full dataset to train multifidelity BNN. In this way, both fidelities are learned together, and the correlations between them are captured due to shared BNN parameters.
To handle the multi-fidelity problem, we adopt the following modifications to Algorithm 1: 1) We train multi-fidelity BNN models using the whole history of simulations, D.
2) The trust-region centering and length updates are based on the post-layout simulation results, i.e., highest-level fidelity results. 3) We determine the candidate selection by modifying the work of [24] where they propose an upper-confidence-bound selection criteria for a single objective BO. We obtain Thompson sampling-based realizations for each fidelity, i.e., {
i (x), for i = 0, 1, . . . , m} where {1, 2} indicate the fidelity level (schematic-level simulations and postlayout level simulations) and then calculate the low fidelity and high fidelity FoM approximations, F oM ( f L (x)) and F oM ( f H (x)) using the corresponding realizations. The candidate selection is queried according to the following utility expression:
where ∆ is the FoM difference between the samples with the best utility at each fidelity. In this step, we take a practical approach to convert two fidelities to each other by defining a reduction term and assign the conservative prediction as the utility value. Finally, the argmin selection is conducted on the candidate utility values to determine the next batch.
4) The current literature on multi-fidelity Bayesian optimization lacks in handling large number of constraints. Therefore, we randomly assign the fidelity (simulation type) for selected candidates and leave the fidelity selection as future work. Note that this action does not prevent us from studying the benefits of multi-fidelity handling of layout-aware sizing. However, we sacrifice potential cost-aware improvements through intelligent fidelity selection.
IV. EXPERIMENTS Experiment Setup and Algorithm Settings: We run our tests using 3 different AMS circuits designed with different technologies. A Two-Stage Folded Cascode Operational Transconductance Amplifier (OTA), and a Strong-Arm Latch Comparator are designed with TSMC 180nm process and used to test schematic-level sizing algorithms. Then, we demonstrate the results for layout-aware algorithms on a Two-Stage Miller OTA. This circuit is designed in TSMC 40nm technology since the layout generator used in this work, MAGICAL, is crafted for TSMC 40nm. The schematic designs for these circuits are included in Figure 4.
We run experiments to study the effectiveness of both of the proposed algorithms. First, we test for the schematic-level sizing algorithm, which is given by Algorithm 1, and we refer to our Bayesian Neural Network Based Bayesian Optimization algorithm as "BNN-BO". Then, we run tests for our postlayout performance-based sizing algorithm. Since we utilize a multi-fidelity BNN for this task, we will refer to this algorithm as "MF-BNN-BO".
We implemented several state-of-the-art baseline algorithms to compare and quantify the quality of our proposed algorithms. We selected the baseline algorithms to cover the different categories of approaches. We list the compared baseline algorithms as follows: 1) A differential evolution global optimization algorithm (DE), 2) Bayesian Optimization with weighted expected improvement (BO) [5], and, 3) RLbased sizing algorithm, DNN-Opt [15]. All algorithms are implemented using Python. We implemented DNN-Opt via PyTorch [25], Bayesian Optimization algorithm is implemented using BoTorch [26] package and BNN-BO and MF-BNN-BO are implemented using PyTorch and Hamiltorch [27] packages.
We configured BNN-BO and MF-BNN-BO to evaluate a batch of q = 8 designs in parallel. For fairness, DNN-Opt and BO are also configured to do parallel evaluations. Both our algorithms use 200 HMC samples to train BNN models. All BNN models are feedforward neural networks with 2 hidden layers and 100 nodes at each hidden layer. Trust-region is initiated with L = 0.8 and L min and L max are chosen to be 0. TABLE I: Schematic-Level Sizing Optimization Statistics Circuit Name Folded Cascode OTA Strong-Arm Latch Comparator Algorithm DE BO DNN-Opt BNN-BO DE BO DNN-Opt BNN-BO success rate 10/10 7/10 10/10 10/10 7/10 1/10 9/10 10/10 # of simulations 3200 340 151 82 2800 >500 154 68 Min power (mW ) 0.75 0.88 0.64 0.60 3.02 3.67 2.45 2.5 Max power (mW ) 1.53 1.43 0.8 0.75 4.1 3.67 2.66 2.55 Mean pow. (mW ) 1.14 1.19 0.72 0.69 3.44 3.67 2.54 2.52 Modeling time (h) NA 30 0.6 1.5 NA 17 0.3 0.7 Simulation time (h) 54 2.7 2.7 2.7 72 3.6 3.6 3.6 Total runtime (h) 54 32.7 3.3 4.2 72 20.6 3.9 4.3 Fig. 7: Strong-Arm Latch Comparator Optimization circuits suggests that BNN-BO can achieve feasible solutions in all and it uses the smallest number of simulations to achieve this. Compared to Differential Evolution (DE), BNN-BO can find feasible solutions using up to 40x less number of simulations. Compared to the closest baseline algorithm, DNN-Opt, BNN-BO reduces the simulation time for finding similar results by up to 55%, proving its high efficiency. It also demonstrated in Table I that, on average, the final design proposed by BNN-BO draws up to 40% less power. The only disadvantage of BNN-BO to DNN-Opt is the modeling time as DNN-Opt maintains a single DNN model to approximate all performance metrics. Note that all reported times consider the full simulation budget (500 new samples). Therefore, although it takes longer time for BNN-BO to do a single iteration, the required real time for BNN-BO to find a feasible solution is still smaller than other approaches.
In addition to experiment statistics, we further include the FoM convergence curves of both tests in Figure 6 and Figure 7. The y-axis in the graphs represents the total constraint violation; therefore, FoM=0 represents a feasible solution. We observe that, compared to DNN-Opt, BNN-BO has 65% and 33% smaller area under the curve for Folded Cascode OTA and SA Latch Comparator, respectively. Layout-Aware Design Automation: In order to demonstrate the importance of layout effects on the final performance, we perform experiments on a Miller OTA circuit designed in 40nm technology (Fig. 4). The optimization problem has 17 independent design variables and the optimization problem is defined as follows: minimize Power s.t. DC Gain > 45 dB Settling Time < 100 ns CMRR > 55 dB Saturation Margins > 50 mV PSRR > 55 dB Unity Gain BW. > 40 MHz Out. Swing > 1 V RMS Noise < 400 uV rms Static error< %2 Phase Margin > 60 deg.
Obtaining the post-layout performance of the Miller OTA is around 9 times more expensive than obtaining the schematiclevel performance. Therefore this experiment is to prove the efficiency by utilizing multiple information sources. We initialize all algorithms with 50 high-fidelity random samples, and MF-BNN-BO has additional 50 samples from low-fidelity source (schematic-level simulations). We demonstrate the FoM evolution for the rest of the optimization steps in Figure 8. We observe that our Multi-Fidelity BNN algorithm provides even more efficiency compared to already efficient BNN-BO. Our analysis shows that the area under the curve is 45% smaller for MF-BNN-BO compared to BNN-BO. Further, we observe that BNN-BO's average best solution after 150 high-fidelity iterations is surpassed by MF-BNN-BO only using 84 simulations. This also implies close to 45% improved efficiency due to utilizing correlations between the schematic-level evaluations and post-layout level evaluations. Note that there is an equal number of schematic-level simulations while running MF-BNN-BO that are not reflected in Figure 8. Considering these simulations, the time efficiency is slightly reduced to around 38%. This efficiency figure serves as a lower-bound since we leave the improvements on fidelity selection as a future work.
In this work, we presented Bayesian Neural Networkbased solutions for schematic-level analog sizing automation and post-layout performance optimization. We targeted the scalability issue of the learning-based automation methods and provided a sample efficient optimization flow. We demonstrated the efficiency of the proposed approaches on academic benchmarks. Compared to the state-of-the-art, we improved the sizing automation efficiency by up to 45%. The Multi Fidelity BNN algorithm analysis proved that utilizing cheaper (schematic-level) simulations reduces the need for expensive (post-layout) simulations considerably, further boosting the efficiency.
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