skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.


This content will become publicly available on November 1, 2025

Title: Interfacial Momentum Matching for Ohmic Van Der Waals Contact Construction
Abstract The difficulty of achieving ohmic contacts is a long‐standing challenge for the development and integration of devices based on 2D materials, due to the large mismatch between their electronic properties and those of both traditional metal‐based and van der Waals (vdWs) electrodes. Research has focused primarily on the electronic energy band alignment, while the effects of momentum mismatch on carrier transport across the vdWs gaps are largely neglected. Graphene‐silicon junctions are utilized to demonstrate that electron momentum distribution can dominate the electronic properties of vdWs contacts. By judiciously introducing scattering centers at the interface that provide additional momentum to compensate the momentum mismatch, the junction conductivity is enhanced by more than three orders of magnitude, enabling the formation of high‐quality ohmic contacts. The study establishes the framework for the design of high‐performance ohmic vdWs contacts based on both energy and momentum matching, which can facilitate efficient heterogeneous integration of 2D–3D systems and the development of post‐CMOS architectures.  more » « less
Award ID(s):
2238564
PAR ID:
10574488
Author(s) / Creator(s):
; ; ; ; ; ; ; ;
Publisher / Repository:
Wiley
Date Published:
Journal Name:
Advanced Electronic Materials
ISSN:
2199-160X
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. Abstract Van der Waals semiconductors (vdWS) offer superior mechanical and electrical properties and are promising for flexible microelectronics when combined with polymer substrates. However, the self‐passivated vdWS surfaces and their weak adhesion to polymers tend to cause interfacial sliding and wrinkling, and thus, are still challenging the reliability of vdWS‐based flexible devices. Here, an effective covalent vdWS–polymer lamination method with high stretch tolerance and excellent electronic performance is reported. Using molybdenum disulfide (MoS2)and polydimethylsiloxane (PDMS) as a case study, gold–chalcogen bonding and mercapto silane bridges are leveraged. The resulting composite structures exhibit more uniform and stronger interfacial adhesion. This enhanced coupling also enables the observation of a theoretically predicted tension‐induced band structure transition in MoS2. Moreover, no obvious degradation in the devices’ structural and electrical properties is identified after numerous mechanical cycle tests. This high‐quality lamination enhances the reliability of vdWS‐based flexible microelectronics, accelerating their practical applications in biomedical research and consumer electronics. 
    more » « less
  2. Over the past decade, the field of two-dimensional (2D) layered materials has surged, promising a new platform for studying diverse physical phenomena that are scientifically intriguing and technologically relevant. Contacts are the communication links between these 2D materials and the three-dimensional world for probing and harnessing their exquisite electronic properties. However, fundamental challenges related to contacts often limit the ultimate performance and potential of 2D materials and devices. This article provides a comprehensive overview of the basic understanding and importance of contacts to 2D materials and various strategies for engineering and improving them. In particular, we elucidate the phenomenon of Fermi level pinning at the metal/2D contact interface, the Schottky versus Ohmic nature of the contacts and various contact engineering approaches including interlayer contacts, phase engineered contacts, and basal versus edge plane contacts, among others. Finally, we also discuss some of the relatively under-addressed and unresolved issues, such as contact scaling, and conclude with a future outlook. 
    more » « less
  3. Beta gallium oxide (β-Ga2O3) shows significant promise in high-temperature, high-power, and sensing electronics applications. However, long-term stable metallization layers for Ohmic contacts at high temperatures present unique thermodynamic challenges. The current most common Ohmic contact design based on 20 nm of Ti has been repeatedly demonstrated to fail at even moderately elevated temperatures (300–400 °C) due to a combination of nonstoichiometric Ti/Ga2O3 interfacial reactions and kinetically favored Ti diffusion processes. Here, we demonstrate stable Ohmic contacts for Ga2O3 devices operating up to 500–600 °C using ultrathin Ti layers with a self-limiting interfacial reaction. The ultrathin Ti layer in the 5 nm Ti/100 nm Au contact stack is designed to fully oxidize while forming an Ohmic contact, thereby limiting both thermodynamic and kinetic instability. This novel contact design strategy results in an epitaxial conductive anatase titanium oxide interface layer that enables low-resistance Ohmic contacts that are stable both under long-term continuous operation (>500 h) at 600 °C in vacuum (≤10−4 Torr), as well as after repeated thermal cycling (15 times) between room temperature and 550 °C in flowing N2. This stable Ohmic contact design will accelerate the development of high-temperature devices by enabling research focus to shift toward rectifying interfaces and other interfacial layers. 
    more » « less
  4. Atomically thin 2D transition metal dichalcogenides (TMDs), such as MoS2, are promising candidates for nanoscale photonics because of strong light–matter interactions. However, Fermi‐level pinning due to metal‐induced gap states (MIGS) at the metal–monolayer (1L)‐MoS2interface limits the application of optoelectronic devices based on conventional metals due to high contact resistance. On the other hand, a semimetal–TMD–semimetal device can overcome this limitation, where the MIGS are sufficiently suppressed allowing ohmic contacts. Herein, the optoelectronic performance of a bismuth–1L‐MoS2–bismuth device with ohmic electrical contacts and extraordinary optoelectronic properties is demonstrated. To address the wafer‐scale production, full coverage 1L‐MoS2grown by chemical vapor deposition. High photoresponsivity of 300 A W−1at wavelength 400 nm measured at 77 K, which translates into an external quantum efficiency (EQE) ≈1000 or 105%, is measured. The 90% rise time of the devices at 77 K is 0.1 ms, suggesting they can operate at the speed of ≈10 kHz. High‐performance broadband photodetector with spectral coverage ranging from 380 to 1000 nm is demonstrated. The combination of large‐array device fabrication, high sensitivity, and high‐speed response offers great potential for applications in photonics, including integrated optoelectronic circuits. 
    more » « less
  5. null (Ed.)
    Enhancing the functionality of silicon through the integration of other materials such as III-V semiconductors has been recognized as a path to overcoming limitations imposed by characteristics fundamental to silicon's material physics while still capitalizing on properties that have enabled the success of the global integrated circuit industry [1]–[2][3]. High-speed electronic devices, devices with high breakdown voltages, light emitting/detecting devices, and devices for photon control can all be integrated with conventional CMOS to perform specialized electronic or photonic functions if suitable methods for forming such heterogeneously integrated regions are available that provide high yield and are compatible with fabrication processes that occur subsequent to the heterogeneous integration process. Technical challenges include lattice mismatch, thermal expansion coefficient differences, having the capability to form low-resistance electrical contacts using materials that are compatible with CMOS, more generally managing cross-contamination in tools used for front-end-of-line processing after III-V regions are established on the silicon wafers, and thermal management for the heterogeneously integrated devices or circuits. These together create formidable obstacles, but there is also the obstacle of defining a business case for creating hybrid wafer fabs given the applications that would be served by ICs with enhanced functionality. Bringing functions that are off chip onto the chip needs to be justified both technically and financially. 
    more » « less