Introduction

Following the discovery of graphene in 2004. [1] 2D semiconductors quickly gained interest toward electronic device technologies. Signiûcant efforts have surged recently emphasizing the DOI: 10.1002/aelm.202400152 use of 2D semiconductors as the channel material in ultrascaled ûeld-effecttransistors (FETs) to enable scaling beyond the limits of bulk semiconductors (i.e., silicon). [2][3][4][5][6][7][8][9][10] Transition metal dichalcogenides (TMDs) have been widely studied for beyond-Si FETs and CMOS technologies. While early studies focused on back-gated FETs constructed from individual üakes of MoS 2 exfoliated from bulk crystals (heavily doped silicon acting as global back gate), [11,12] new efforts must push toward the use of largearea CVD-grown materials and advanced multi-gate device architectures such as double-gate FETs, [13][14][15] FinFETs, [16] and gate-all-around (GAA) FETs. [17] Indeed, recent efforts have started to explore FETs using CVD-grown 1L-MoS 2 , including individually back-gated, top-gated, and double-gate architectures. For example, recent work from Intel and other [3,[17][18][19][20][21][22] has suggested that 2D TMDs offer a unique opportunity for scaling transistor gate lengths below 10 nm to support the continuation of Moore's Law. In fact, commonly cited semiconductor technology roadmaps such as the IEEE International roadmap for devices and systems (IRDS) [23] proposes the complete replacement of silicon by 2D semiconductors as the channel material by the <0.7 nm= node and beyond (2034 and beyond). It should be noted that in these advanced nodes the choice of insulating materials in the gate stack is equally important and stringent requirements are needed to ensure performance and reliability. [24] First, a scalable device technology requires a small equivalent oxide thickness (EOT) to support good gate control of channel electrostatics in short channel dimensions. At the same time, gate leakage (i.e., current üow across the gate insulator) should be kept at a minimum to maintain low power consumption, and traps (in the oxide and at the semiconductor/oxide interface) should be minimized to achieve good stability and reliability. [10] For modern FETs using 2D semiconducting channels, identifying suitable insulating materials remains a signiûcant challenge and it is crucial to examine existing solutions based on their impact on performance and stability in advanced device architectures. [24] A few previous works have reported subthreshold swing and other performance metrics in double-and top-gate FETs, and recent efforts have studied gate hysteresis and stability in devices using advanced seeding methods for ALD of high-k gate oxides on MoS 2 devices [25] Nonetheless, the effect of EOT scaling on CVD-grown 1L-MoS 2 FETs comparing double-gate and single top-gate remains largely unexplored and is addressed in this work.

In this work, we present an experimental analysis on the performance of double-gate and top-gate FETs fabricated from CVD-grown monolayer (1L) molybdenum disulûde (MoS 2 ) with atomic-layer deposition (ALD) of hafnium oxide (HfO 2 ) high-k gate dielectrics (top and bottom). The analysis compares contact resistance and mobility between double-gate and top-gate device architectures based on extractions from transfer length method (TLM) test structures (i.e., FETs with various channel lengths but consistent contact and gating conûgurations), [8,14,26,27] as well as subthreshold swing and gate hysteresis. Importantly, the analysis of subthreshold swing and gate hysteresis is presented as a function of EOT to establish improvements in performance and stability as EOT is reduced to ≈ 1 nm as dictated by the semiconductor roadmaps for advanced CMOS nodes. We also note that in our electrical characterization of double-gate FETs, both top and bottom gates are biased in common mode conûguration (i.e., held at the same voltage). However, to elucidate the effect of the backgate biasing on device performance we also present data analysis from measurements in independent mode where top and bottom gates are individually biased at different voltages. Here, a reversal in the temperature-dependence of on-state current as a function of increasing back-gate bias indicates an improvement in contactresistance and device performance in double-gate FETs resulting from electrostatic doping/modulation of Schottky junctions in the contact regions. Our measurements also reveal non-uniform gate hysteresis as a function of independent top-and bottom-gate bias, which may be crucial to characterizing and understanding charge trapping phenomena associated with gate hysteresis and to achieving stable and reliable operation of future MoS 2 FET technology. [28][29][30] Lastly, we analyze gate hysteresis using various voltage sweep rates on top-gate devices with two different oxide thicknesses to identify the impact of EOT scaling on device stability.

Results and Discussion

Figure 1a shows an optical image and micrograph of the fullyfabricated wafer that includes arrays of double-gate and top-gate CVD-grown 1L-MoS 2 FETs in a TLM test structure conûguration. A description of the fabrication methods is given in the Experimental Section with more detailed schematics of the processing steps provided in the Supporting Information. A higher magniûcation image in the active channel region of an individual doublegate TLM structure is shown in Figure 1b with the atomistic model depicting the monolayer MoS 2 channel. In our fabrication process, a CVD-grown monolayer of MoS 2 is transferred from the growth substrate onto a Si/SiO 2 wafer prepared with the bottom gate stack (Figure S1, Supporting Information). To ensure the quality of the channel material we conduct Raman spectroscopy before and after transfer. Figure 1c shows the Raman spectra before and after transfer and conûrms negligible degradation to the 1L-MoS 2 ûlm during transfer. Figure 1d FET. In this work, we also refer to single top-gate FETs which were fabricated with an identical process except without the bottom gate stack. Schematic diagrams for the top-gate FETs, compared against the double-gate devices, are provided in the Supporting Information (Figure S3, Supporting Information).

The performance of double-gate and top-gate FETs are ûrst compared based on extractions of contact resistance and mobility using the transfer length method. [26] Here, both the doublegate and top-gate FETs have the same bi-layer top-gate stack with EOT = 2.73 nm (1 nm Al 2 O 3 /10 nm HfO 2 ), and double-gate FETs have an additional bottom-gate stack with a 10 nm HfO 2 gate dielectric. We measure drain-current (I d ) as a function of gate voltage (V g ) for devices with various channel lengths ranging from L = 7000 nm down to 360 nm. The channel width W = 7.6 μm is the same for all devices. Figure 2a plots the current-voltage (I-V) characteristics where drain current is normalized to channel width (units of μA μm -1 ). The x-axis plots the overdrive voltage V ov = (V g -V T ), which is used to ensure the same on-state conditions in our extractions from all device measurements. Thus, for different L we can extract and plot total resistance R = V d /I d at various V ov as shown in Figure 2b (each line corresponds to different V ov ranging from 0.3 to 3 V). Contact resistance (R c ) and sheet resistance (R sh ) are respectively extracted from the extrapolated yaxis intercept and slope of a linear ût to the data points for each V ov . Next, by estimating sheet carrier density as n s = C ins V ov /q, where C ins = ÿ ins /t ins is the oxide/insulator capacitance per unit area above threshold, we plot R c and R sh as a function of n s as shown in Figure 2c. While Figure 2a,b only show measurements from double-gated FETs (for clarity), Figure 2c shows extrac-tions for both double-gate (solid lines with symbols) compared against top-gate (dashed-lines with symbols). The data shows that double-gate FETs achieve better contact resistance compared to top-gated FETs, reaching values as low as ≈30 kΩ-μm. These values are not optimal (IRDS speciûes 220 Ω-μm for the 0.7 nm node), but they are comparable to other reported CVD-grown 1L-MoS 2 FETs, and there is room for improvement based on advanced contact engineering strategies. [8,27,31,32] From sheet resistance we can obtain the mobility as µ con = (qn s R sh ) -1 which is plotted as a function of n s in Figure 2d. The extracted µ con are smaller compared to theoretical values and to values reported on exfoliated samples (better crystallinity), but similar to previous reports on CVD-grown 1L-MoS 2 samples. [33] Nonetheless, these values can be improved with optimized growth recipes and/or using transfer-free methods. [34] We also demonstrate improvements on charge transport properties and device performance in doublegate FETs compared to top-gate FETs. This is discussed below based on temperature-dependent measurements of on-state current at different top-and bottom-gate biasing (see Figure 4). Overall, the CVD-grown 1L-MoS 2 double-gate FETs perform better than top-gated FETs in terms of contact and sheet resistance, mobility, and on-state current; This is attributed to the effect of bottom-gate bias on the Schottky junctions at the source/drain contact regions.

To further elucidate the effect of the bottom-gate biasing on device performance we also analyze data from measurements in independent mode where top and bottom gates are individually biased at different voltages. These measurements were conducted over a wide temperature range to provide a better understanding [15,[40][41][42] MBE [13] and exfoliated samples. [40,43] EOT scaling and double-gate architecture achieves improvements in SS. Each symbol/color combination indicates a different device measurement. DG = double gate, BG = bottom gate only, TG = top gate only.

of charge injection and charge transport in the double-gate FETs under the effect of independent bottom and top-gate bias. [35][36][37] Figure 3a plots drain-to-source current (I ds ) as a function of topgate voltage g,top ) at different ûxed bottom-gate voltages (V g,bot ) ranging from -3 to 3 V in steps of 0.6 V, and at a temperature of 300 K. Similarly, Figure 3b plots I ds versus V g,top at ûxed V g,bot and at a temperature of 77 K. For each combination of temperature and V g,bot we extract on-state current (I on ) at a ûxed top-gate overdrive voltage V ov,top = V g,top -V T = 1.6 V. The on-state current is plotted in Figure 3c as a function of temperature and for different V g,bot . We observe a reversal in the temperature-dependence of I on as V g,bot is increased from -3 V up to 3 V. For V g,bot = -3 V the onstate current increases with increasing temperature, whereas for V g,bot = 3 V the on-state current decreases with increasing temperature. This is indicative of a transition in the dominant/limiting charge injection and transport mechanism in the double-gate FET with increasing bottom-gate bias. We note that the bottomgate extends under the source/drain regions (see Figure 1), therefore V g,bot can modulate the MoS 2 energy bands (through electrostatic doping) and consequently the Schottky barriers formed at the contacts. For negative V g,bot , large energy barriers exist at the Schottky junctions between source/drain contacts and the MoS 2 channel and these are further enhanced by the electrostatic doping resulting from V g,bot . Thus, the injection of charge carriers, in this case electrons into the conduction band, is limited by thermionic emission over the barrier and increasing temperatures leads to more charge carrier injection and therefore more on-state current as evidenced by the experimental results of I on . On the other hand, for large positive V g,bot the electrostatic doping effect results in narrower energy barriers at the Schottky contacts, lessening the limitation of thermionic emission as more electrons can tunnel through these barriers into the conduction band. As a result we obtain larger I on . This also results in the aforementioned reversal in the temperature dependence on I on . Now, the dominant mechanism limiting charge üow is scattering in the channel region which generally intensiûes with increasing temperature (e.g., more phonon scattering) translating to a reduction in I on with temperature. Overall, the electrostatic doping effect of V g,bot improves device performance in double-gate FETs compared to single top-gate devices, in addition to other more well-known improvements related to better gate control of the channel electrostatics.

Within the same set of experiments on double-gate FETs with independent top and bottom-gate bias we characterize gate hysteresis using dual-sweep (sweep up and down) measurements of V g,top at ûxed bottom gate voltages. These are plotted in Figure 3d (room temperature), where we show the current on a logarithmic scale to better observe hysteresis and the subthreshold region. For clarity, we only show the data for three different values of V g,bot , and a plot of the full range of biases is provided in the Supporting Information (Figure S2, Supporting Information). Interestingly, for a ûxed V g,top or corresponding I ds , the bottom-gate bias has a signiûcant impact on the magnitude of gate hysteresis. Similar effects were reported previously on graphene FETs [38] based on carrier-defect energy decoupling. [39] Here we deûne gate hysteresis as the shift in V g,top during sweep down versus sweep up to achieve the same value of I ds . When extracted for all different values of V g,top and over a large range of I ds , regions of large and small hysteresis are identiûed as illustrated by the contour plot shown in Figure 3e. We note that this observation of bottom-gate bias dependence may be crucial to better understand charge trapping phenomena associated with gate hysteresis and to achieve stable and reliable operation of future MoS 2 FET technology. [38] A closer look at the I d versus V g characteristics provides more evidence of improvements in double-gate FETs compared to single top-gate FETs, as shown in Figure 4a. The double-gate FET shows larger on-state current, larger ON/OFF ratio, and better (smaller) subthreshold swing. We note that both devices in this comparison have the exact same top gate stack with EOT = 2.73 nm. The double-gate FETs show larger hysteresis as a result of having two dielectric layers (top and bottom) that can contribute to charge trapping effects (in contrast, single top-gate FET only has one gate dielectric on top). Nonetheless, a key advantage of a double-gate architecture is the improvement in gate control of the channel electrostatics and can be quantiûed by the subthreshold swing (SS). In Figure 4b we plot SS as a function of drain current for sweep-up and sweep-down comparing doublegate and top-gate FETs. The double-gate FET in better (smaller) SS over the full range of I d which extends more than 5 orders of magnitude in the subthreshold region. For EOT = 2.73 nm we achieve a minimum SS of ≈300 mV dec -1 in the topgate FET and ≈200 mV dec -1 in the double-gate FET (1.5× improvement). These numbers are larger than the ideal 60 mV decat room temperature (300 K), but are comparable to other reports on CVD-grown 1L-MoS 2 FETs with ALD gate dielectrics. Additional plots of I d -V g and SS-I d characteristics are shown for devices with varying EOT in the supporting information (Figure S4, Supporting Information).

For benchmarking purposes, Figure 4c compares our results in top-gate and double-gate FETs against previous reports including CVD, [15,[40][41][42] molecular beam epitaxy (MBE) [13] and mechanically exfoliated MoS 2 , [40,43] in double-gate, top-gate, and back-gate FETs. Moreover, the results are shown as a function of EOT to establish the impact of EOT scaling on performance. EOT scal-ing potentially leads to improved gate control, reduction of short channel effect, improved threshold voltage control, enhanced carrier transport, and suppression of charge-trapping effects and associated phenomena. Ultimately, EOT scaling can help make the most of 2D channel materials toward ultra-scaling of MOS-FET technology. Our double-gate FETs with EOT scaling down to ≈1.5 nm and top-gate FETs with EOT scaling down to ≈1 nm show signiûcant improvements in SS down to ≈ 120 mV dec -1 . We emphasize that this is one of the best subthreshold swing performances reported on 1L-MoS 2 FETs, other than in MBE and exfoliated samples. The fact that MBE and mechanical exfoliation can achieve reduced defect density suggests that the quality/crystallinity of the channel plays a signiûcant role in subthreshold swing performance together with the gate dielectric and interface quality. Nonetheless, mechanical exfoliation is not a scalable process (can only achieve small isolated üakes) and MBE is more costly, difficult to scale to large wafer-size, and incompatible with direct growth on amorphous substrates. [44] We also include results from FETs fabricated on CVD-grown monolayer MoS 2 directly on SiO 2 (i.e., no transfer) [42] showing improvement in SS (≈80 mV dec -1 ), but limited to high-temperature processing.

Also included in this plot are bottom-and double-gate FETs prepared by mechanical exfoliation of MoS 2 and mechanical exfoliation (and stacking) of hexagonal boron nitride (h-BN) as the gate dielectric. [43] As a crystalline insulator, h-BN has the potential to provide well-deûned van der Waals (vdW) interfaces with 2D semiconductors. [24] In this regard, previous work has reported interface trap densities (D it ) as low as ≈10 9 cm -2 eV -1 in h-BN/MoS 2 . [45] This can result in nearly ideal SS as well as signiûcant enhancement of channel mobility resulting from the suppression of trap-induced charged-impurity scattering effects. Nonetheless, limitations in bandgap and dielectric properties can impact EOT scalability for h-BN and high leakage is expected for small EOT≈1 nm. [46] As a result, most previous demonstrations are based on thick exfoliated h-BN samples (EOT > 8 in Figure 4c). Thus, h-BN is considered a promising insulator for 2D-material-based devices that do not require extreme scaling. Nevertheless, mechanical exfoliation is not considered a scalable process and large-area CVD-grown h-BN requires further optimization to achieve comparable defect densities. Interestingly, the existence of native defects in CVD-grown h-BN ûlms has led to signiûcant efforts toward h-BN resistive-switching memory based on recoverable soft breakdown phenomena. [47,48] As noted for the I-V characteristics in both double-gate and top-gate MoS 2 FETs (Figures 3d, 4a) measured using dual voltage sweeps (i.e., sweep up and sweep down), charge-trapping effects are evident as gate hysteresis (i.e., voltage shift in the sweep up vs sweep down measurements). Careful examination of charge trapping effects is crucial to understand the long-term reliability/stability and performance of 2D MoS 2 FETs. Previous work on MoS 2 FETs has used measurements of gate hysteresis in their I d -V g characteristics to map out the oxide traps with widely distributed time constants. [29,30] By varying the voltage sweep range as well as the sweep rate, extractions of gate hysteresis were used to obtain the density and energy distribution of oxide traps and to explain the hysteresis dynamics in relation to positive and negative bias-temperature instability (PBTI, NBTI). However, the impact of EOT scaling on gate hysteresis in CVD-grown 1L MoS 2 FETs remains largely unexplored. Nonetheless, it is anticipated that by reducing the physical thickness of the gate oxide (i.e., reducing EOT), the oxide capacitance increases, and the effect of trapped charge is lowered (ΔV≈ΔQ/C ox ), so gate hysteresis will be smaller. To examine the EOT-dependence of gate hysteresis we have conducted a series of I d -V g dual sweeps with varying sweep rates on top-gated MoS 2 FETs with three different EOT. This allows to observe the effect of oxide traps with different time constants and provide a more conclusive comparison between devices of different EOT.

In Figure 5a we plot the I d -V g characteristics of top-gated MoS 2 FETs with EOT = 2.73 nm measured using dual voltage sweeps with varying sweep rates ranging from 0.45 to 0.005 V s -1 . Here, sweep rate is deûned as V step /t step where V step is the voltage step in the sweep and t step is the time step. We note that gate hysteresis is smaller in these devices compared to earlier work using signiûcantly larger EOT ≈ 10 nm (23.5 nm Al 2 O 3 ). [29] In this work, the top-gate stack includes a 1 nm oxidized Al seeding layer and 10 nm HfO 2 dielectric layer (EOT = 2.73 nm) prepared by ALD. Other EOT (1.57 and 1 nm) are achieved with thinner HfO 2 (5 and 3 nm). The results in Figure 5a show that reducing the sweep rate (slower sweep) results in larger hysteresis, but also in an slight shift to more positive voltages for both sweep-up and sweep-down measurements. This positive shift is consistent with positive-bias-temperature instability (PBTI) attributed to charge build-up contributed by slow electron traps that become negatively charged (electron capture) for positive gate bias [29] A more quantitative analysis is obtained by extracting threshold voltage from sweep up (V + T ) and from sweep down (V - T ) measurements. The extractions of threshold voltage are plotted in Figure 5b as a function of sweep frequency deûned as f = 1/t sweep where t sweep is the total sweep time. The plot shows threshold voltage extractions for EOT = 2.73, 1.57, and 1 nm. From the extracted threshold voltages, the gate hysteresis width is calculated as 5c plots hysteresis width as a function of sweep frequency for all three different EOTs. The main observations are 1) gate hysteresis increases with reducing sweep frequency as more traps with slower time constants can contribute to charge trapping; 2) gate hysteresis peaks and then drops below a certain frequency (f ≈10 -3 Hz) consistent with previous observations and models [49] This is evident for EOT = 2.73 nm, but further investigation is needed to conûrm a peak in gate hysteresis for smaller EOT; 3) gate hysteresis is smaller for smaller EOT (appears to be directly proportional to EOT). These results provide initial insights to the impact of EOT scaling on gate hysteresis in CVD-grown 1L-MoS2 FETs with high-k ALD oxides. The results indicate favorable trends in EOT scalability in relation to gate hysteresis. Nonetheless, further studies with larger samples of EOT should provide a more complete picture on the relationship between EOT and V H . Moreover, in addition to gate hysteresis, other considerations toward EOT scaling are crucial to ensure device performance and reliable 2D FET operation, such as gate leakage. In our experiments, we did not detect signiûcant gate leakage for EOT = 2.73 and 1.57 nm, but we measured a gate current density of ≈1.5 × 10 -2 A cm -2 for EOT = 1 nm. This level of gate current density is near the low-power of 10 -2 A cm -2 and consistent with previous work on MoS 2 /HfO 2 . [24,46]

Conclusion

We report a comprehensive analysis of FETs constructed from CVD-grown 1L-MoS 2 with HfO 2 gate dielectrics. This study compares top-gate against double-gate FETs (DGFETs), extending beyond most previous studies that used exfoliated (few-nm thick) MoS 2 üakes, instead focusing on large-area wafer-scale methods. We measure signiûcant improvements in performance for double-gate FETs (larger ON/OFF ratio, larger ON-state current, smaller sub-threshold swing) compared to single top-gate FETs. Moreover, we quantify the impact of EOT scaling, crucial toward improved electrostatics required for next-generation nanoscale transistors, on subthreshold swing and gate hysteresis. This was previously unexplored for CVD-grown 1L-MoS 2 FETs, especially in double-gate device architectures that can facilitate ultra-scaling for future CMOS technology nodes. We also provide new insight about performance improvement in DGFETs attributed to improved electrostatic gate control (lower subthreshold swing) and improved charge-injection across source/drain contacts and the channel (larger I on ). Finally, we experimentally demonstrate a reduction in gate hysteresis with reduced EOT indicating favorable scaling trends with respect to MoS 2 /HfO 2 gate-stack stability.

Experimental Section

Device Fabrication: CVD-grown monolayer MoS 2 was purchased from 6Carbon Technology (Shenzhen) and was transferred to a Si/SiO 2 substrate using a conventional wet-transfer method. In the case of double-gate FETs, the Si/SiO 2 substrate was initially prepared with a bottom gate stack using standard lithography, deposition, and liftoff (gate electrode), and ALD (HfO 2 gate dielectric). After transferring the CVD-grown 1L-MoS 2 , the channel region was patterned by dry etching, and source and drain contacts (5 nm Ti/25 nm Au) were fabricated using photolithography, deposition, and liftoff. Here, different channel lengths are prepared (used in TLM experiments) as determined by different distances between source and drain contacts (360, 850, 1600, 3200, and 7000 nm). Next, a seeding layer (1 nm Al 2 O 3 ) was used to improve subsequent ALD ûlm adhesion and uniformity. To prepare the seeding layer, <1 nm Al was deposited by e-beam evaporation at a rate of 0.1 A s -1 and was treated thermally to convert into Al 2 O 3 . Then, ALD deposition of HfO 2 (3, 5 nm, or 10 nm) was done at 180 °C to achieve conformal deposition. An additional lithography step is then used to prepare the top gate by e-beam evaporation and lift-off. Finally, the bottom gate and source-drain pad regions are made accessible using a masked dry-etching step to remove the various ALD high-k dielectric layers. More details about the fabrication and a process üow diagram is included in the Supporting Information (Figure S1, Supporting Information).

Electrical Measurements: Electrical measurements were conducted on a Lakeshore CRX-VF cryogenic probe station combined with a Keysight b1500a semiconductor parameter analyzer. Temperature controlled I-V measurements were performed using various source measure units (SMUs) connected at a vacuum of 10 -6 torr with ZN50R-CVT probes (uninterrupted variable temperature probes). All measurements with varying sweep rates were conducted using a Keithley 4200 semiconductor characterization system (SCS) using SMUs programmed with ûxed timing parameters.