Zhuang, Jinming, Yang, Zhuoping, Ji, Shixin, Huang, Heng, Jones, Alex, Hu, Jingtong, Shi, Yiyu, and Zhou, Peipei. SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. Retrieved from https://par.nsf.gov/biblio/10610981.

Zhuang, Jinming, Yang, Zhuoping, Ji, Shixin, Huang, Heng, Jones, Alex, Hu, Jingtong, Shi, Yiyu, & Zhou, Peipei. SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. Retrieved from https://par.nsf.gov/biblio/10610981.

Zhuang, Jinming, Yang, Zhuoping, Ji, Shixin, Huang, Heng, Jones, Alex, Hu, Jingtong, Shi, Yiyu, and Zhou, Peipei. "SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration". Country unknown/Code not available: The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2024). https://par.nsf.gov/biblio/10610981.

@article{osti_10610981,
place = {Country unknown/Code not available}, title = {SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration}, url = {https://par.nsf.gov/biblio/10610981}, abstractNote = {}, journal = {}, publisher = {The 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2024)}, author = {Zhuang, Jinming and Yang, Zhuoping and Ji, Shixin and Huang, Heng and Jones, Alex and Hu, Jingtong and Shi, Yiyu and Zhou, Peipei}, }