Analog circuit topologies' design has historically relied heavily on manual effort and domain expertise. This approach not only results in a lengthy design cycle but also restricts the discovery of novel analog circuit topologies. Emerging technologies, such as AI, 5G/6G, and quantum computing, impose stringent performance demands, creating a need for innovative analog circuit topologies beyond the capabilities of well-established designs. To support the advancement of these technologies, a critical question arises: how can we efficiently explore and invent circuit topologies that might achieve unprecedented performance, surpassing what human expertise alone has accomplished? Recently, AIdriven methodologies for analog hardware design have shown promise in accelerating the design cycle across various stages of the design flow [1]- [10]. However, existing research [11]- [13] mainly addresses the analog circuit topology synthesis problem, focusing on meeting specific design objectives by selecting or reusing known topologies or sub-blocks from existing designs. In contrast, the discovery problem of novel analog circuit topologies remains underexplored due to its abstract and complex nature.
In this work, we tackle the novel circuit topology discovery problem due to its scientific significance and potential for This work is partially supported by NSF #2416375 and NSF #2526432. breakthrough innovations. Existing approaches have achieved great progress in topology discovery for certain types of analog circuits. CktGNN [1], a pioneering effort, employs a variational autoencoder (VAE) with a two-level graph neural network (GNN) to learn and generate diverse operational amplifier (Op-Amp) topologies. Similarly, Karahan et al. [14] propose an inverse design approach for the rapid synthesis of complex RF-to-terahertz (THz) matching networks by generating various electromagnetic (EM) structures. However, these approaches are limited in versatility and discovery efficiency without the ability to discover diverse types of analog circuit topologies while targeting certain performance preferences.
To address these challenges, we introduce EVA, an efficient and versatile generative engine for discovering novel analog circuit topologies. To achieve great versatility, EVA proposed a bottom-up generation framework that uses a decoder-only transformer to generate diverse analog designs from scratch, starting from a VSS pin and sequentially predicting the next device pin connection. Instead of training with performancelabeled topology from scratch, EVA is first pre-trained on a diverse set of unlabeled circuit topologies to learn the circuit connectivity. In this way, the model itself has already achieved a basic level of discovery efficiency by generating valid topology and setting a great foundation for finetuning. For targeted discovering specific circuit types with high performance within limited attempts, EVA proposed two fine-tuning strategies based on proximal policy optimization (PPO) [15] and direct preference optimization (DPO) [16] with a limited number of labeled topology thanks to the foundation laid by the pretrained model. In this way, EVA is able to achieve great training sample efficiency and discovery efficiency without wasting evaluation time on irrelevant or low-performing circuits. Our key contributions are as follows:
• EVA is a versatile generative engine that can discover diverse, novel analog circuit topologies by sequentially predicting device pin connections, starting from VSS.
• EVA pretrains a decoder-only transformer on an unlabeled dataset of circuit topologies, enabling efficient generation of valid circuits and significantly improving training sample efficiency by reducing the reliance on performance-labeled samples during fine-tuning.
• EVA enhances discovery efficiency by fine-tuning with PPO and DPO on a small set of performance-labeled topologies, focusing on high-performance circuits and minimizing irrelevant evaluations.
• Experimental results across various analog circuit types demonstrate EVA's advantages in topology validity, novelty, versatility, sample efficiency, and discovery efficiency.
Analog circuit topology synthesis aims to develop circuits that meet design goals using established topologies or subblock topologies. Existing ML methods primarily address the issue of data scarcity when building models capable of automating analog circuit design. AnalogCoder [11] highlights that while large language models (LLMs) have been extensively trained on Python code, they lack exposure to the SPICE netlist, the industry-standard format for describing analog circuits. To bridge this gap, they employ domain-specific prompt engineering, enabling LLMs to generate PySpice code that can be seamlessly converted into SPICE netlists without additional training-thus maximizing training sample efficiency. Similarly, Artisan [12] translates SPICE netlists into natural language, allowing the development of domainspecific foundation models for analog circuit design, even with limited data. On the other hand, LaMAGIC [13], a finetuned masked language model (MLM), has been proposed to generate power converter circuit topologies by predicting the connections between predefined nodes. However, most current approaches to analog circuit topology design rely heavily on existing circuit topologies or subblock structures, which constrains their ability to discover novel topologies.
Novel analog circuit topology discovery aims to identify novel, non-existent circuit topologies that could potentially expand our understanding of analog circuits. Existing ML approaches have primarily focused on discovering designs at two distinct levels, each restricted to a specific type of analog circuit. CktGNN [1] addresses the schematic level by generating a variety of Op-Amp topologies. This method adopts a top-down graph generation approach but limits the design scope to sub-blocks without incorporating device-level details. While this constraint simplifies the generation process and ensures valid topologies (e.g., avoiding floating nodes), it also restricts the diversity of circuits that can be explored. Karahan et al. [14], on the other hand, focus on the physical level, employing an inverse-design approach using binary matrices to generate unintuitive EM structures for RF-to-THz matching networks. However, applying this method to schematic-level design is challenging, as the complexity of analog circuit topologies-due to the wide variety of device types and numbers-cannot be adequately captured by a binary matrix representation. Beyond versatility limitations, these methods are also constrained by inefficient discovery processes. Both approaches lack target discovery capabilities, relying heavily on trial and error, which leads to substantial evaluation overhead from real-world simulators due to frequent low-performance circuit assessments. To mitigate this, Karahan et al. proposed training a forward model to predict performance for specific EM structures, a promising direction but one that demands over 600k performance-labeled EM structures, making it extremely sample inefficient. III. EVA FRAMEWORK EVA in Figure 2 is an efficient and versatile generative engine designed to discover novel analog circuit topologies. It uses a device pin-level graph representation [17], sequentialized as an Eulerian circuit, to capture all possible connections in a compact format while retaining critical structural information. EVA leverages a decoder-only transformer architecture, pre-trained on diverse analog circuit topologies, to generate circuits from scratch by sequentially predicting device pin connections. Through fine-tuning strategies such as PPO and DPO, EVA efficiently generates high-performance circuit topologies with minimal labeled data, targeting specific circuit types and desired performance.
Existing approaches to schematic-level analog circuit topology discovery generally formulate the problem as a graph generation task, where each circuit topology is represented as a device-level graph with nodes corresponding to individual devices (e.g., NMOS transistors) [1]. EVA, in contrast, adopts a device pin-level graph representation as shown in Figure 1 where each node corresponds to an individual device pin (e.g., NM1 G, NM1 D, NM1 S, and NM1 B) [17]. Since analog circuit topologies are typically sparse-most devices connect only to their immediate neighbors-traditional adjacency matrices are inefficient, as they waste space representing nonexistent edges [1], [13]. To address this, EVA sequentializes the graph as an Eulerian circuit [17], a path that traverses each directed edge exactly once before returning to the starting node (e.g., VSS). Unlike prior approaches that limit graph structures to directed acyclic graphs (DAGs) [1]-which cannot universally represent all analog topologies-the Eulerian circuit approach is more versatile, capable of representing any analog circuit that can be modeled as a finite connected undirected graph.
EVA employs a customized domain-specific tokenizer to encode and decode sequences for pretraining a decoder-only transformer to discover a wide range of analog circuit topologies. Each token in EVA's tokenizer corresponds either to a device pin (e.g., NM1 G, NM1 D, NM1 S, NM1 B) or to a circuit-level pin for the overall analog topology (e.g., VIN1, VOUT1, VDD, VSS). To ensure the model can generalize across circuit topologies with varying numbers and types of devices, EVA uses a data-driven approach to scan the entire dataset and determine device limits. A special token, "Truncate," is introduced to handle padding when sequences of varying lengths are processed.
With this domain-specific tokenizer, EVA pre-trains a decoder-only transformer to predict the next device pin within a circuit topology. Unlike typical language model pretraining, which crops sequences randomly from text, EVA ensures that each sequence corresponds to a single complete circuit topology. Given an corpus of tokens U = {u 1 , . . . , u n } representing one circuit topology, EVA maximizes the standard language modeling objective [18] to train the model.
TABLE I: Rank score definitions for PPO finetuning Reward Definition 1.0 High performance relevant valid circuit 0.5 Low performance relevant valid circuit -0.5 Irrelevant valid circuit -1.0 Invalid circuit
Here, k represents the size of the context window, and the conditional probability P is modeled by a neural network with parameters Θ. During the generation phase, the model is initially provided with just one context token, "VSS," which serves as the starting node for all Eulerian circuits. From this single token, the model generates the rest of the sequence, completing it to represent an entire circuit topology.
The pre-trained model in EVA has developed foundational knowledge of circuit connections across various circuit types, enabling it to achieve baseline discovery efficiency by generating valid circuits. To further enhance its ability to efficiently generate high-performance circuits within limited attempts, EVA fine-tunes this model to align with human preferences for both type and performance. Building on the foundation provided by pretraining, EVA can leverage a small set of performance-labeled topologies to guide generation towards high-performance designs. EVA introduces two fine-tuning strategies that balance training stability and overfitting.
1) Proximal policy optimization: EVA adopts PPO [15] as one of its reinforcement learning with human feedback (RLHF) strategies. PPO uses limited labeled samples to train a reward model as a labeler, enabling the pre-trained model to generate new samples, which are then labeled by the reward model for fine-tuning based on human preferences. Specifically, EVA utilizes a Plackett-Luce ranking model [19] for sequence reward, ranking multiple classes as shown in Table I. The reward model combines a rule-based checker with a multiclass classifier: it first checks if a generated circuit is valid (i.e., simulatable with default sizing) and then classifies circuit type and performance. To train this multiclass classifier, a limited set of circuit topologies is initially labeled for type and performance. For instance, if EVA aims to discover highperformance Op-Amps, only Op-Amps are relevant, while other types are irrelevant. The figure of merit (FoM) determines whether relevant circuits are high-performance, with Otsu's method [20] setting the FoM threshold. Once labeled, EVA adds a three-output linear layer on top of the final transformer layer, outputting a reward value after softmax.
With the trained reward model, PPO performs optimization as shown in Algorithm 1. The major components of PPO are defined as follows: Agent: The agent is the policy model à θ , which is the pretrained model fine-tuned to align with human preferences. EVA adds a value head to it, which consists of a simple linear layer that takes hidden states as input and outputs a single scalar per token. The value function provides an estimate of the expected cumulative reward from any given state. end for 11: end for Environment: The environment is the reward model R φ . This environment assigns rewards based on whether generated sequences meet criteria defined in Table I. Action: The action is discrete by selecting a token y t (i.e., device-pin) from a pre-defined tokenizer's look-up table based on the current context x t (i.e., generated sequence). State: The state is the current context x t . Reward: Starting from the initial state x 0 (i.e., "VSS"), the RL agent takes a discrete action by predicting the next token y t given the current state x t in each time step t, and the environment returns a reward r t at that step. EVA defines the PPO reward function as follows:
Here, R φ (x, y), is the reward model's score that measures how well the entire sequence aligns with preference defined in Table I. The second term is a penalty that discourages à θ from deviating too much from à θ ref , with ³ controlling the strength of this penalty. The reference model à θ ref is a fixed version of the pre-trained language model that the policy model was initially based on.
In PPO, the entire sequence or circuit topology acts as a trajectory, with the objective of optimizing the policy model à θ to generate sequences that maximize the expected accumulated reward via the advantage A and the policy loss L policy . Concurrently, PPO refines value prediction V bnew using the value loss L value . As shown in Algorithm 1, each epoch begins with PPO generating rollouts (sequences) using the policy model, and the reward model R φ assigns rewards r, where each r corresponds to a rollout. PPO then performs minibatch optimization. The policy loss L policy is designed to maximize the expected advantage of the actions taken by the agent while preventing large, destabilizing updates to the policy.
Here, advantages
) measure how much better (or worse) an action at time t is compared to the expected outcome calculated from value function V b (x bt+1 ). L represents the probability ratio between the current and previous policies during minibatch optimization. With the clip objective, the policy loss in PPO strikes a balance between exploiting the current advantage-encouraging the model to increase the probability of actions that yield higher expected rewards-and maintaining stable, incremental updates to the policy. In PPO, the value loss L value is calculated to enhance the accuracy of the model's value function.
The value loss L value is the squared difference between the newly predicted value V bnew (x bt ) and the target return G t . The G t = A t + V b (x bt ) represents the total expected reward for the trajectory from t onward, including the estimated value of future states. By incorporating both immediate and future rewards, G t is a robust target for updating the value function.
2) Directed preference optimization: PPO is effective in preventing overfitting by continually generating new training data [21]. However, its complexity and stability issues arise from its sensitivity to hyperparameters and dependence on a reward model. To address these challenges in a simpler and more stable way, EVA introduces a finetuning strategy based on DPO [16]. Unlike PPO, which requires a separate reward model to label newly generated data, DPO finetunes the pretrained model using a static dataset with expert-labeled data. This approach enhances stability, as the training labels are accurate and unaffected by the reward model's classification reliability. Moreover, DPO's objective function is simplified compared to PPO, with only a single hyperparameter, ³, which controls the extent of à θ deviation from the reference model.
DPO utilizes the Bradley-Terry model [22] as its preference framework, focusing on pairwise comparisons (win or lose) rather than the multi-rank model employed in PPO. Specifically, optimizing L DPO guides the pre-trained model to identify analog circuit topologies that maximize the expression log π θ (yw|x) πref (yw|x) -log π θ (y l |x) πref (y l |x) , thus encouraging it to generate "winning" topologies while discouraging "losing" ones. Given the complexity of human preferences for analog circuit topologies, EVA still relies on human experts to label circuit topologies according to a multi-rank model, as defined in Table I. For any four data points where each belongs to a unique class, EVA transforms these into six unique winlose pairs for DPO training (e.g., High performance relevant valid circuit > Low performance relevant valid circuit, High performance relevant valid circuit > Irrelevant valid circuit, etc.).
Datasets: The EVA circuit dataset comprises 3470 unique and real-world topologies across 11 circuit types: Op-Amps, LDOs, Bandgap references, Comparators, PLLs, LNAs, PAs, Mixers, VCOs, Power converters, and Switched Capacitor Samplers from public resources [23]- [28]. Each circuit's performance was assessed through circuit simulation, and a corresponding label was assigned based on its performance metrics and label definition defined in Table I.
EVA training setup: EVA splits the topology dataset into training and validation sets with a 9:1 ratio, ensuring the validation topologies remain unseen during training. EVA uses a depth-first search (DFS) to identify the Eulerian circuit for each topology. To prevent overfitting, it permutes DFS traversal order, creating multiple unique Eulerian circuits per topology, expanding the original 3470 topologies to 234393 sequences. EVA's generation model is a decoder-only transformer with 6 layers, 6 attention heads, and 11.825 million parameters, with a vocabulary size of 1029 and maximum sequence length of 1024. The reward model architecture is detailed in Section III-C1. Baseline: To compare with EVA, we select AnalogCoder [11], Artisan [12], and LaMAGIC [13] as the representative ML baselines for analog circuit topology synthesis and select CktGNN [1] as the representative ML baselines for novel analog circuit topology discovery at the schematic level. The differences between these methods and EVA are discussed in Section II. We follow original work to produce their results. Evaluation tasks and metrics: We evaluate generative quality across the following metrics: (1) Validity: An unsized circuit is valid if it can be simulated in SPICE without errors (e.g., floating or shorting nodes). Each method generates 1000 topologies, and we report the percentages that are valid. (2) Novelty: Each method generates 1000 topologies, and we measure the percentage of them that are different from the topologies in the dataset. To quantify the topology difference, We converted them into graphs and computed the maximum mean discrepancy (MMD) [29] between these and real-world graphs converted from our circuit dataset. (3) Versatility: The number of distinct analog circuit types generated indicates versatility. ( 4) Training sample efficiency: Efficiency is evaluated by comparing the number of labeled topologies (i.e., with known performance) required for training. ( 5) Discovery efficiency: Given the time cost of performance evaluation, each method only generates 10 topologies, and we report the maximum FoM (e.g., gain, bandwidth, power for Op-Amps) after sizing with a genetic algorithm and SPICE evaluation.
We first perform an ablation study to evaluate the necessity of both pretraining and fine-tuning. As shown in Figure 3, PPO results reveal that the pretrain-only model establishes a solid foundation in generating irrelevant valid circuits (score = -0.5) and low-performance relevant valid circuits (score = 0.5). However, it lacks the ability to specifically target high-performance relevant valid circuits (score = 1), necessitating further fine-tuning. Similar observations are evident in DPO results, where the pretrain-only model shows no strong preference for winning topologies, as indicated by 0 reward accuracy. This suggests the model predominantly generates losing topologies during generation, i.e., log π θ (yw|x) πref (yw|x) < log π θ (y l |x) πref (y l |x) . In contrast, the finetune-only model lacks the foundational understanding of circuit connectivity, making it challenging to effectively train on a limited number of labeled samples to generate valid topologies. For PPO, EVA's vast design space (1029 1024 ), dominated by invalid topologies, leads to an extremely sparse reward signal (i.e., most rewards are suboptimal). As a result, guiding the finetune-only model to discover high-performance relevant valid circuits from scratch becomes infeasible using a simple reward model. On the other hand, DPO results indicate that even an untrained model can achieve reward accuracy exceeding 50%, highlighting a limitation in this metric. Specifically, the metric only measures the preference for generating winning topologies, log π θ (yw|x) πref (yw|x) > log π θ (y l |x) πref (y l |x) , without assessing the actual generation quality of winning topologies à θ (y w | x) or losing topologies à θ (y l | x). This limitation is further validated in Table II, where EVA (DPO only) fails to generate any valid topologies. In conclusion, EVA can effectively target highperformance relevant valid circuits only through a combination of pretraining and finetuning.
TABLE II: Performance comparison between EVA and existing analog circuit topology generation work. Evaluation metric Validity (%) ↑ Novelty Versatility ↑ # of labeled topology ↓ FoM@10 [12], [13] ↑ Diff circuit (%) ↑ MMD ↓ Op-Amp Power converter Op-Amp Power converter AnalogCoder [11] 66.1 0 0 7 11 N/A 232.1 N/A Artisan [12] 82 0 0 1 14000 N/A 12769.5 N/A CktGNN [1] 68.5 93 0.313 1 10000 N/A 311.3 N/A LaMAGIC [13] 75 3 0.001 1 N/A 132000 N/A 2.2 EVA (Pretrain) 84 99 0.0518 11 0 0 274.1 2.5 EVA (PPO only) 0 N/A N/A 11 a 850 362 N/A N/A EVA (DPO only) 0 N/A N/A 11 a 850 362 N/A N/A EVA (Pretrain+PPO) 94 99 0.0509 11 a 850 362 13647.2 3.3 EVA (Pretrain+DPO) 83 99 0.0491 11 a 850 362 13763.8 3.4
a Targeting another circuit type requires redo fine-tuning, which takes less than an hour on an A100 GPU.
We compare PPO and DPO for EVA fine-tuning in terms of training stability and generation quality. PPO, an online RL method, dynamically generates new topologies and samples rewards from the environment, but its training instability stems from the stochastic reward signal r bt , leading to noisy advantage estimates A t and oscillations in L policy . In contrast, DPO, an offline RL method, optimizes the relative log-likelihood between winning and losing topologies using static preference data, avoiding noisy rewards. For generation, PPO demonstrates superior validity by optimizing for both preference and reward-based quality through continuous exploration of new topologies. This enables it to overcome degeneration issues and produce valid, diverse outputs that outperform the pretrained model. DPO, however, shifts the model's preference to high-performance topologies in the dataset without learning from new data, leading to degeneration in validity. This degeneration is characterized by a reduction in both winning and losing topology generation likelihoods in Figure 4, with the latter declining faster. At low learning rates, this degeneration is manageable, and our results focus on these settings, as shown in the Figure 4 and Table II. Higher learning rates, while not depicted, can cause the model to collapse, generating repetitive tokens. Despite these limitations, DPO excels in targeted discovery, producing higher-FoM topologies within 10 attempts and achieving lower MMD values, which indicate a closer resemblance to real-world circuits.
Finally, we compare EVA with prior methods: Validity: EVA demonstrates higher validity than previous methods. Top-down approaches like CktGNN and LaMAGIC rely on predefined representations, which limit their generalization to other circuit types and restrict the range of topologies they can be trained on. In contrast, EVA's universal circuit representation and bottom-up generation framework enable pretraining on diverse analog circuits with more training data. Novelty: EVA excels in discovering novel circuits compared to AnalogCoder and Artisan, which primarily reuse existing topologies or subblocks. LaMAGIC is confined to a small design space (fewer than 4 devices), limiting its ability to discover new topologies. While CktGNN and EVA both support larger circuits (around 20 and 60 devices, respectively), Ckt-GNN is trained on synthetic datasets, which lack critical realworld features. EVA, trained on real-world circuits, improves MMD by over 6× and generates around 99% novel circuits. Versatility: EVA outperforms Artisan, CktGNN, and LaM-AGIC, which can only design one type of circuit. While AnalogCoder supports seven circuit types, it is limited to a synthesis library of just 20 topologies. EVA, trained on a dataset with 11 circuit types and over 3000 topologies (minimum 30 per type), demonstrates unparalleled versatility. Sample efficiency: Unlike prior work that typically uses performance-labeled topology to train a model from scratch, EVA first pretrains on an unlabeled dataset to build a strong foundation in circuit connectivity. This enables efficient finetuning with only a small labeled dataset, achieving up to 364× greater training sample efficiency compared to other methods. Discovery efficiency: CktGNN and EVA (Pretrain) lack targeted discovery, often producing low-performance circuits within 10 attempts. AnalogCoder's synthesis library only contains simple circuits, which also limits the FoM of the circuit it synthesized. After finetuning, EVA is able to align with human preference and target high-performance circuits within limited attempts. Combining the foundation knowledge it learned from all sorts of analog circuit types during pretraining, EVA is able to discover unseen topologies with superior FoM compared to dedicated synthesizers like Artisan and LaMAGIC, excelling in both Op-Amp and power converter.
In this work, we propose EVA, a versatile and efficient generative engine for discovering novel analog circuit topologies. EVA employs a bottom-up generation framework using a decoder-only transformer to sequentially predict device pin connections, starting from a VSS pin. By pretraining on an unlabeled dataset of circuit topologies, EVA establishes a strong foundation for topology generation, enabling finetuning with minimal performance-labeled data. Through finetuning strategies based on PPO or DPO, EVA achieves high discovery efficiency, targeting high-performance circuits while minimizing wasteful evaluations. EVA paves the way for AIdriven discovery in analog circuit, unlocking unprecedented potential for innovation in next-generation technologies.