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Title: Panel-Scale Reconfigurable Photonic Interconnects for Scalable AI Computation
Panel-scale reconfigurable photonic interconnects on a glass substrate up to 500-mm × 500-mm or larger are envisioned by proposing a novel photonic switch fabric that enables all directional panel-edge-to-panel-edge reach without active repeaters while offering high communication bandwidth, planar-direction reconfigurability, low energy consumption, and compelling data bandwidth density for heterogeneous integration of an in-package artificial intelligence computing system on a photonic interposer exceeding thousands of centimeters square. The proposed approach focuses on reconfigurable photonic interconnects, which are integration-compatible with commercial processor chiplets and 3-D high-bandwidth memory stacks, to create a novel panel-scale heterogeneously integrated package enabled by high-capacity wavelength-division-multiplexing optical data links using advanced optical modulators, broadband photodetectors, novel optical crossbar switches with multilayer waveguides, and on-chip frequency comb sources.  more » « less
Award ID(s):
2045935 2410053 2217453
PAR ID:
10677884
Author(s) / Creator(s):
 ;  ;  ;  
Publisher / Repository:
IEEE
Date Published:
Journal Name:
IEEE Open Journal of the Solid-State Circuits Society
Volume:
5
ISSN:
2644-1349
Page Range / eLocation ID:
437 to 453
Subject(s) / Keyword(s):
Accelerator, artificial intelligence (AI), bandwidth density, chiplet-to-chiplet communication, edge coupler, energy efficiency, frequency comb, heterogeneous integration, high-bandwidth memory (HBM), interconnect, interposer, large language model (LLM), micro bump, micro-ring resonator (MRR), optical communication, packaging, power delivery, power density, processor, racetrack resonator, silicon photonics, through-silicon via (TSV), through-substrate via (TSV), wavelength-division-multiplexing (WDM).
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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