More Like this

1. Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS ₂ FETs

   https://doi.org/10.1002/aelm.202400152  

   Patoary, Naim Hossain; Mamun, Fahad Al; Xie, Jing; Grasser, Tibor; Sanchez_Esqueda, Ivan (November 2024, Advanced Electronic Materials)

   Abstract 2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS₂) with atomic layer deposition (ALD) of hafnium oxide (HfO₂) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS₂flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS₂DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS₂DGFETs compared to standard top‐gate FETs. 

   more » « less
2. Optimization of High‐κ HfO ₂ Transistor Dielectrics by Atomic Layer Deposition as an Enabler of Novel Thin‐Film Circuits and Sensors

   https://doi.org/10.1002/apxr.202500191  

   Forouzmehr, Matin; Pourkheirollah, Hamed; Leite, Fabio; Howard, Elin; Behera, Sunil Kumar; Tewari, Amit; Laakso, Jarmo; Lahtonen, Kimmo; Laia, Cesar_A T; Parola, A Jorge; et al (January 2026, Advanced Physics Research)

   ABSTRACT This study explores the integration of atomic layer deposited (ALD) HfO₂dielectric films with solution‐processed In₂O₃semiconductor channel, thin‐film transistors (TFTs) for a silicon chip‐free temperature sensor label. The inclusion of the HfO₂high‐κ dielectric permits reduced voltage operation of the sensor label. HfO₂films are deposited by atomic layer deposition (ALD) at three different hot source temperatures (80°C, 90°C, 100°C), with XPS revealing improved stoichiometry and O/Hf ratios of 1.75, 1.92, and 1.95, respectively, as temperature increases. MOSCAP measurements show improved oxide/semiconductor interface with higher deposition temperatures. The extracted dielectric constants (ε_r≈ 18.5–18.8) correspond to an equivalent oxide thickness (EOT) of about 3.1 nm, consistent with optimized high‐κ film formation. To enhance drain current, a reduced 7.5 nm HfO₂film thickness is used, achieving higher current but reducing yield by 30% due to increased leakage probability in ultrathin films. A voltage divider circuit is developed to integrate an electrochemical thermal sensor, TFT, and an irreversible visual indicator (IVI), allowing for temperature monitoring with a resistivity change of three orders of magnitude at 8°C. The circuit is powered by a 60 mF supercapacitor array providing approximately 0.21 J of available energy, resulting in IVI activation within 40 min at measured activation currents of 20 µA. The system demonstrates potential for low‐voltage, energy‐efficient, silicon‐free sensor labels in applications such as food safety and healthcare monitoring. 

   more » « less
3. Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation

   https://doi.org/10.1038/s41699-022-00353-1  

   Song, Jingfeng; Qi, Yubo; Xiao, Zhiyong; Wang, Kun; Li, Dawei; Kim, Seung-Hyun; Kingon, Angus I; Rappe, Andrew M; Hong, Xia (December 2022, npj 2D Materials and Applications)

   The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS₂transistors back-gated by single-layer polycrystalline PbZr_0.35Ti_0.65O₃. The devices exhibit current switching ratios up to 8 × 10⁶within an ultra-low gate voltage window of$$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ $V_g=\pm 0.5$V and subthreshold swing (SS) as low as 9.7 mV decade⁻¹at room temperature, transcending the 60 mV decade⁻¹Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics. 

   more » « less
4. Threshold voltage control with high-temperature gate-oxide annealing in ultrawide bandgap AlGaN-channel MOSHFETs

   https://doi.org/10.35848/1882-0786/ac8bc4  

   Mollah, Shahab; Hussain, Kamal; Mamun, Abdullah; Alam, Md Didarul; Chandrashekhar, MVS; Simin, Grigory; Khan, Asif (September 2022, Applied Physics Express)

   Abstract We report threshold voltage (V_TH) control in ultrawide bandgap Al_0.4Ga_0.6N-channel metal oxide semiconductor heterostructure field-effect transistors using a high-temperature (300 °C) anneal of the high-kZrO₂gate-insulator. Annealing switched the polarity of the fixed charges at the ZrO₂/AlGaN interface from +5.5 × 10¹³cm⁻²to −4.2 × 10¹³cm⁻², pinningV_THat ∼ (−12 V), reducing gate leakage by ∼10³, and improving subthreshold swing 2× (116 mV decade⁻¹). It also enabled the gate to repeatedly withstand voltages from −40 to +18 V, allowing the channel to be overdriven doubling the peak currents to ∼0.5 A mm⁻¹. 

   more » « less
5. Lithium-ion electrolytic substrates for sub-1V high-performance transition metal dichalcogenide transistors and amplifiers

   https://doi.org/10.1038/s41467-020-17006-w  

   Alam, Md Hasibul; Xu, Zifan; Chowdhury, Sayema; Jiang, Zhanzhi; Taneja, Deepyanti; Banerjee, Sanjay K.; Lai, Keji; Braga, Maria Helena; Akinwande, Deji (December 2020, Nature Communications)

   Abstract Electrostatic gating of two-dimensional (2D) materials with ionic liquids (ILs), leading to the accumulation of high surface charge carrier densities, has been often exploited in 2D devices. However, the intrinsic liquid nature of ILs, their sensitivity to humidity, and the stress induced in frozen liquids inhibit ILs from constituting an ideal platform for electrostatic gating. Here we report a lithium-ion solid electrolyte substrate, demonstrating its application in high-performance back-gated n-type MoS₂and p-type WSe₂transistors with sub-threshold values approaching the ideal limit of 60 mV/dec and complementary inverter amplifier gain of 34, the highest among comparable amplifiers. Remarkably, these outstanding values were obtained under 1 V power supply. Microscopic studies of the transistor channel using microwave impedance microscopy reveal a homogeneous channel formation, indicative of a smooth interface between the TMD and underlying electrolytic substrate. These results establish lithium-ion substrates as a promising alternative to ILs for advanced thin-film devices. 

   more » « less