In this study, we explore the operation and performance of electrolyte-gated junctionless III-V nanowire (NW) transistors featuring compositionally graded In
The progression of modern electronics is fundamentally tied to enhancements in both active and passive materials, in addition to advances in device engineering [1,2]. Innovations in materials such as conductors, semiconductors, dielectrics, and passive components, when integrated with cutting-edge device architectures, not only enhance the performance, cost-efficiency, and miniaturization of integrated circuits (ICs), but also pave the way for emergent applications [3]. These applications span across next-generation displays, sensors, and interfaces between humans and machines [4]. Significantly, transistors, varying in structure and operational modes, remain crucial to the foundational framework of electronic devices.
In metal-oxide-semiconductor field-effect transistors (MOSFETs), the channel dimension is a critical performance indicator for the central processing unit (CPU) [5]. Commercial products have achieved channel dimensions as small as 5 nm, while prototypes at the forefront of technology have successfully reduced this to 1 nm [6]. Transistor scaling is critical to sustaining the historical pace of increased logic device density and improved performance per chip. However, continued scaling imposes major obstacles such as managing the exponential rise in gate tunneling leakage current, controlling short-channel effects, and variability at nanometer dimensions [7]. To overcome the leakage challenges, the adoption of a high-κ dielectric solution reduces carrier mobility [8]. However, high-κ dielectric-based gate stacks present other obstacles, including bias temperature instability, complex processing and integration, challenges in achieving high-quality interfaces, and ensuring material stability without undesirable reactions [9][10][11].
The field of iontronics focuses on regulating the electrical properties and operational capabilities of electronic devices by harnessing the dynamics and organization of ions [12]. Electric double-layer (EDL) gating using ionconducting electrolytes enables ultra-high charge carrier densities (i.e., > 10 14 cm -2 ), which exceed the capability of oxide dielectrics before reaching breakdown [13]. Due to the induction of high fields and significant capacitance densities, EDL gating has also emerged as an exceptionally effective method for revealing novel physical phenomena and material properties in two-dimensional (2D) crystals in the fields of spintronics [14] and superconductivity [15,16]. Moreover, this method is applied to nanotubes [17,18], as well as semiconductor nanowires made from group III-V [19] and II-VI materials. This showcases the flexibility of ion-conducting materials in terms of their physical and chemical compatibilities with other solid-state systems, as well as their capability to operate across a wide range of electrochemical conditions [20]. Therefore, EDL gating is regarded as an effective method for achieving field-effect control of semiconductor nanostructures [21][22][23][24]. Another advantage of EDL gating is that the strength of the gating is only weakly dependent on the distance between the channel and gate, which allows for flexibility in the placement of the gate electrode and enables the possibility to achieve gate-allaround geometries [26,27].
To date, significant progress has been made using EDL gating on 2D semiconductors [12,25]. However, fabricating integrated circuits using 2D transistors and scaling devices to nanoscale dimensions, while ensuring film thickness uniformity, thermal stability, and long-term reliability, remains challenging [26]. On the other hand, III-V semiconductors (e.g., In x Ga 1-x As) offer higher carrier mobilities, compositionally tunable bandgaps, and ease of integration with silicon by leveraging epitaxial growth of nanostructures [27]. Their excellent transport properties enable high frequencies and high power efficiencies unattainable by silicon, making them highly attractive candidates for next-generation electronics and photonics [28]. Controlling III-V semiconductor nanostructure devices via field-effect, such as in nanowire transistor configurations, offers transformative potential for both fundamental research and practical technological applications. Nanowire transistors offer several compelling advantages over conventional planar devices. Their gateall-around geometry provides superior electrostatic control over the channel, enabling better scaling and suppression of short-channel effects that plague planar MOSFETs [3]. Additionally, the quasi-1D structure of nanowires allows for effective strain engineering and the integration of highmobility channel materials like III-V compounds, leading to performance enhancements [27]. Furthermore, nanowire transistors offer potential benefits in terms of reduced power consumption, increased drive current, and better subthreshold swing, making them promising candidates for future low-power and high-performance electronics [29]. With their superior electrostatic integrity, ability to leverage novel channel materials, and prospects for energy-efficient operation, nanowire transistors represent a promising device architecture for continued scaling and performance improvements in the nanoelectronics era.
State-of-the-art advancements in electrolyte-gated fieldeffect transistors (FETs) have primarily focused on single nanowire (NW) devices, which offer a valuable platform for studying electrostatic gating effects at the nanoscale. Prete et al. [30] explored the performance of InAs NW-based EDL FETs, highlighting their potential for low-voltage operation and efficient current modulation due to strong electrostatic coupling at the electrolyte/semiconductor interface. Similarly, Lieb et al. [19] investigated the ionic liquid gating of InAs NW-FETs, demonstrating enhanced charge carrier accumulation and improved transconductance compared to conventional oxide-gated counterparts. These studies underscore the effectiveness of electrolyte gating in modulating carrier densities and improving electrostatic control in single NW devices. However, extending such architectures beyond single NW-based transistors toward more scalable and manufacturable device configurations remains an important goal in optimizing for practical applications. This study builds upon these advancements by exploring the influence of electrolyte gating in a heterostructured junctionless nanowire architecture, with comprehensive TCAD modeling to assess performance scalability.
The context of applicability of this novel device architecture lies in low-power electronics, where energy-efficient operation is crucial for scaling down devices in applications such as wearable sensors and portable computing [31]. Furthermore, the enhanced electrostatic control provided by electrolyte gating makes them highly suitable for highperformance switches, where precise modulation of carrier density is necessary [32]. This technology also holds significant promise for applications in quantum computation, where minimizing power consumption while maintaining device scalability is essential for practical quantum information processing [33].
In this work, we simulate the operation and performance of electrolyte-gated junctionless III-V NW transistors composed of compositionally graded In x Ga 1-x As channels. We utilize a two-dimensional simulation approach, in order to balance the need for computational efficiency with the necessity to capture the essential physical behaviors and characteristics of the NW device. Despite the dimensional reduction, this approach allows us to conduct meaningful simulations and derive insights that are relevant to the understanding and optimization of NW-based device performance. To mimic the EDL that is induced at the electrolyte/semiconductor interface, we consider Fermi-Dirac statistics by a numerical method to reproduce associated charge densities of EDL transistors, and add a 1 nm interfacial oxide (HfO 2 ) layer to capture the electrostatics of the EDL and prevent charge transfer between the electrolyte and channel regions, following the methodology of Koch et al. [31]. We optimize the channel configuration by tuning the heterostructured In x Ga 1-x As NW composition and doping profile. Next, we perform device simulations comparing fixed and bias-dependent conduction band and valence band effective density of states. We benchmark the EDL double-gated device structure against a conventional HfO 2 -gated device structure. We demonstrate an I ON /I OFF ratio of 10 6 for the EDL-gated device with bias-dependent effective conduction and valance band density of states, with subthreshold slope of 60 mV/dec, and threshold voltage of 0.31 V, operating at a low drain voltage of 0.3 V. This represents two orders of magnitude improvement in I ON /I OFF ratio compared to conventional junctionless oxide-gated NW transistors while operating at an ideal subthreshold slope of 60 mV/dec, demonstrating that EDL gating provides improved electrostatic integrity in III-V NW-based configurations.
Optimizing electrolyte-gated junctionless III-V nanowire transistors aims to achieve high-performance, low-power electronic devices suitable for advanced logic applications. The current state-of-the-art demonstrates that these transistors can effectively suppress short-channel effects and operate efficiently at reduced supply voltages, owing to the superior electrostatic control inherent to their gateall-around architectures. This optimization is crucial for developing next-generation electronics that demand highspeed operation with minimal energy consumption. The electrolyte improves transistor characteristics by forming an EDL at the electrolyte/semiconductor interface, which acts as a highly efficient nanoscopic capacitor. This ultra-high capacitance significantly enhances electrostatic control over the channel, enabling effective carrier modulation at much lower gate voltages. As a result, electrolyte gating allows for improved subthreshold slopes and higher ON/OFF current ratios compared to traditional oxide-gated transistors, making it a promising approach for next-generation low-power electronics. The electrolyte improves transistor characteristics by forming an EDL at the electrolyte/semiconductor interface that is usually 1 nm or less thick, which induces capacitance densities on the order of 1-10 uF/cm 2 and significantly enhances electrostatic control over the channel, enabling effective carrier modulation at much lower gate voltages [12,22]. As a result, electrolyte gating allows for improved subthreshold slopes and higher ON/OFF current ratios compared to traditional oxide-gated transistors, making it a promising approach for next-generation low-power electronics.
Previously, Koch et al. [31] and Mohammadi et al. [32] independently proposed a generalized model for an electrolytegated transistor in Sentaurus TCAD, wherein the electrolyte was treated as an intrinsic semiconductor using Fermi-Dirac statistics. Since TCAD cannot distinguish between ions and electrons/holes [33], the voltage-dependent cation (i.e., hole) concentration is expressed as its corresponding effective density of states (DOS) and is summarized by the following relationship,
where N V , E G , and k B T are the effective DOS for holes, electrolyte bandgap, and thermal energy, respectively. Unlike previous studies where DOS was estimated based on the properties of water [31,32] and Si [33], finite element modeling was conducted here using COMSOL Multiphysics (v6.0) to extract (gate) voltage-dependent ion densities in order to provide a closer representation of the intended experimental material systems and a more accurate estimation of the DOS. The solid electrolyte was modeled as a 50 nm × 50 nm metal-electrolyte-metal capacitor, with PEO: LiClO 4 as the solid electrolyte. The modified Poisson-Nernst-Planck (mPNP) equation is used to model the ion transport and is given by, where c + (c_), D + (D_), and z + (z_) are the local ionic concentrations (ions/m 3 ), diffusivities (m 2 /s), and charge states of cations (anions), respectively. Elementary charge (C) and
(1)
thermal energy (J) are represented by q and k B T, respectively. The local potential (V) was obtained by solving the Poisson's equation, ∇. -0 ∇V = q c + -c -, where 0 is the vacuum permittivity and is relative dielectric permittivity. Kilic et al. [34] derived the steric repulsion factor (γ) to account for packing density of the ions, which is defined as:
where a + (a_) represents the diameter of the cation (anion).
For the capacitor model, the cation and the anion were assumed to have equal sizes and diffusivities to simplify the finite element analysis calculations. For a Li-like ion, diameter, a, of 0.2 nm and diffusivity, D, of 10 -12 cm 2 /s were used in the simulations [35,36]. The permittivity, ε, of the electrolyte was selected as 10, based on experimental values [37]. Cation concentrations, p, were extracted from the COM-SOL model for voltages between 0 and 1.3 V, and directly input to TCAD for full electrolyte-gated transistor simulations. For example, p = 2.65 × 10 19 cm -3 was extracted from COMSOL at 1.3 V for E G = 1.5 eV, and an initial bulk ion concentration, C i , of 0.564 mM was used, which corresponds to N V = 10 32 cm -3 . The bandgap was chosen to satisfy the following boundary condition of the Poisson-Boltzmann equation, with φ as the intrinsic electric potential [38],
This can be interpreted as follows: the energy required to move an electron in the electrolyte, from the valence to conduction band, is significantly larger than the combined potential and thermal energies, indicating a material with low electrical conductivity and ensuring that only ionic conduction is accounted for. Similarly, C i = 0.564 mM (i.e., 5.64 × 10 -4 mol/L), which corresponds to a total cation concentration of p ≃ 3.4 × 10 17 cm -3 under no gate bias, implying sufficient ions are available for effective gating. Chung et al. [33] modeled a SiNW FET gated with a KCl solution of concentration varying from 0.04 mM to 40 mM and demonstrated charge concentrations as high as ~ 5 × 10 17 cm -3 induced in the channel; note that the results extend to any 1:1 electrolyte, like LiClO 4 , for example. Similar works have shown effective gating with electrolyte concentrations as low as 10 -4 mM [35,36,41,42].
The simulations in this study were conducted using the 2D Silvaco's Atlas software (Version 5.22.3.R). Classical carrier transport using drift-diffusion (DD) is being examined. For the modeling of all device parameters, we used Fermi-Dirac
statistics for carrier distribution calculations, as it is necessary to account for the characteristics of very highly doped semiconductors, such as bandgap narrowing and reduced mobility effects. To model the carrier generation and distributions, we considered the Shockley-Read-Hall (SRH) recombination model [40,41]. It is well-known that the presence of heavy doping in semiconductors results in bandgap reduction [42], and in our simulations we considered the Del Alamo bandgap narrowing model [43]. We utilize the Caughey and Thomas expression to accurately describe carrier transport in the DD mode, modeling mobility field properties and ensuring a seamless transition between low-field and high-field zones. This method has also been utilized in the simulation of III-V transistors [44]. To model the inversion layer of the MOSFET devices, we considered the Lombardi CVT model, which considers the transverse field, doping, and temperature dependencies of carrier mobility [45].
Within the scope of TCAD, the material parameters pertinent to iontronics are notably absent, and the characterization of the electrostatic properties at the electrolyte/ semiconductor boundary remains insufficiently defined. This issue is compounded by an insufficiency of the principles governing the behavior of ions within the electrolyte material. Mohammadi et al. [32] proposed a method to adopt an electrolyte material in TCAD by including a new material with the same properties of the electrolyte. This process can be accomplished by conceptualizing the electrolyte as an intrinsic semiconductor and employing Fermi-Dirac statistics. Indeed, upon selecting suitable parameters for the DOS and the bandgap of the intrinsic semiconductor, the Fermi-Poisson equation aligns as documented in Ref. [24] and [39]. In an intrinsic semiconductor, the energy discrepancies between the valence band, conduction band, and quasi-Fermi level can be approximated by assuming that the energy difference is approximately half the bandgap. Hence, in the electrolyte material, the holes can be described as "cations" and electron as "anions", as expressed in Eq. ( 5).
Here, N V and N C are effective DOS for the valance and conduction bands, respectively, E F is the Fermi energy level, while E C and E V are conduction and valance band edge energies, respectively. Since Silvaco cannot differentiate between the holes and cations, a set of fixed DOS values were used to simulate the charge carriers.
To model the electrostatic coupling at the electrolyte/ semiconductor interface, Koch et al. [31] included a thin oxide layer between the electrolyte and semiconductor to create a double-layer capacitor, with the semiconductor (5)
� being ion-impermeable. Furthermore, ion permeation into the III-V semiconductor channel is highly unlikely due to the atomic scale integrity of the interface. The InAs lattice structure is sufficiently compact, and the surface is defectfree and atomically abrupt, eliminating any potential pathways for ion diffusion. This is supported by the findings of Abrand et al. [46], which demonstrate that InAs nanowires grown via localized self-assembly exhibit coherent lattice extension with well-defined heterointerfaces. The highquality interface minimizes unintended charge trapping and enhances electrostatic control, making it highly suitable for electrolyte-gated transistor applications. Additionally, the operating voltage range is carefully selected to avoid any electrochemical reactions, such as ion permeation, ensuring stable operation at room temperature. This range has been experimentally validated in previous studies, demonstrating the ability to achieve high carrier densities without inducing electrochemistry [47][48][49].
It is essential to model the oxide layer such that its capacitive effects are minimal compared to the capacitance of the EDL. Consequently, the capacitance of the Helmholtz plane's thin layer becomes predominant, influencing the overall capacitance, surface potential, and current in the devices and preventing charge transfer between electrolyte and the channel. This setup results in ion accumulation within approximately 1 nm of the interface between the electrolyte and the III-V channel material. As a result, the device exhibits a high capacitance that governs the transistor's drain current, independent of the electrolyte thickness [49].
While this study employs a TCAD-based approach to model electrolyte-gated transistors by treating the electrolyte as an intrinsic semiconductor, alternative methodologies have been proposed. For instance, Bandiziol et al. [50] developed a site-binding charge model within TCAD to simulate electrolyte/semiconductor interfaces, incorporating a Stern layer and surface reactions. This method provides a more explicit treatment of surface chemistry effects at the interface in addition to the electrostatic gating effect. However, the approach assumes a fixed site-binding charge model, which may not fully capture bias-dependent redistribution of ions in the electrolyte region.
In contrast, our methodology focuses on the electrostatic gating effect and incorporates bias-dependent ionic concentrations extracted from COMSOL simulations, providing a more direct representation of the dynamic electrostatic modulation at the electrolyte/channel interface under variable biasing conditions. This ensures a more accurate depiction of charge carrier tuning under variable gate biases. Additionally, by tuning the conduction and valence band DOS values within TCAD, our approach aligns with the Fermi-Poisson equation to effectively represent the formation of the EDL. While Bandiziol et al.'s method can be useful for applications requiring a strong emphasis on chemical interface interactions, our approach is particularly advantageous for evaluating the electrostatic response of electrolyte-gated transistors in dynamic operating conditions [50]. Recently, Woeppel et al. demonstrated a COMSOL model with selfconsistently coupled ion and charge transport, which captures steady state carrier densities, but has limitations in extracting dynamic changes in carrier density or channel current (i.e., transistor transfer curves) [35]. Future extensions of this work could explore the integration of both methodologies to refine electrolyte/semiconductor interaction modeling further. It is important to note that the previous studies used as reference, either model their electrolyte as water with high permittivity resulting in high effective DOS, have selected material parameters to satisfy Eqs. ( 4) and ( 5), and/or involve electrochemical reactions. In comparison, the simulation parameters used in our methodology have been experimentally verified through Hall effect measurements and provide a more practical representation of the solid electrolyte's behavior.
By implementing the above physical models, we have simulated single gate (SG), double-gate (DG), and dual electrolyte-gated transistor configurations, which are shown in Fig. 1(a), (b), and (c), respectively. All device dimensions and material parameters used for the simulation are listed in Table 1 and Table 2, respectively. Note that for all device structures explored here, the gate length and channel length are considered equal, such that L g = L ch .
To systematically assess the impact of gate control on electrostatic integrity, we compare single-gate (SG) and double-gate (DG) configurations in InAs nanowire transistors, varying the channel thickness between 100 and 50 nm. The transfer characteristics are presented in Figure S1 of the Electronic Supplementary Material (ESM). The SG configuration with a channel thickness of 100 nm demonstrated minimal difference between the ON and OFF state currents due to its limited gate controllability. Conversely, the SG configuration with the channel thickness of 50 nm exhibited an I ON /I OFF of 10 3 and a subthreshold slope (SS) of 87.6 mV/ dec, indicative of improved electrostatic control. Although the SG device with the smaller channel thickness shows better gate controllability, the I ON /I OFF is very low and the SS is not near the ideal value of 60 mV/dec. So, we simulated the device with DG configuration and channel thickness of 50 nm and achieved I ON /I OFF of 10 4 with near-ideal SS of 64.1 mV/dec. It is reported in literature that heterostructured III-V MOSFETs outperform traditional MOSFETs in several key aspects [51,52]. By utilizing different semiconductor materials for the channel and barrier layers, higher electron mobility enabling faster switching speeds and lower power consumption are achieved [52]. Additionally, heterostructured MOSFETs often exhibit steeper subthreshold slopes, allowing for efficient operation at lower voltages, which is essential for power efficiency by utilizing the tunneling phenomenon [53][54][55]. Utilizing a DG heterostructure configuration with In x Ga 1-x As source, InAs channel, and In x Ga 1-x As drain, as depicted in Fig. 1(b), we investigated its transfer characteristics with a static composition of x = 0.5 in the source and varying the drain composition (x = 0.25, 0.50, and 0.75), while maintaining a doping level of 10 17 cm -3 throughout all segments. As displayed in Fig. 2(a), the transfer characteristics across all drain compositions showed a uniform threshold voltage value (Vth) of 0.31 V and uniform SS value of 62.4 mV/dec, with additional performance metrics listed in the inset of Fig. 2. Remarkably, each configuration attained an I ON /I OFF ratio of 10 5 , which represents one order of magnitude improvement compared to purely InAs DG structures with the same doping level, as shown in Figure S1 of the ESM. Insights into the uniformity of these characteristics are provided through consideration of the energy band diagrams shown in Figure S2 of the ESM. The band diagrams demonstrate that a barrier at the drain side of the transistor limits charge collection at the drain contact, contributing to similar transfer characteristics across various drain material compositions. This observation, detailed in Figure S2 of the ESM, shows that a uniform doping profile throughout the device inhibits the formation of a charge reservoir in the DG device configuration.
To improve carrier collection and enhance the overall performance of the device, we investigated different doping profiles and drain material compositions and we evaluated their impacts on the MOSFET transfer characteristics, as shown in Fig. 2(b). This analysis aims to identify optimal doping configurations that maximize ON/OFF ratio and improve switching efficiency. In Fig. 2 and henceforth throughout this paper, we use the following notation convention when referring to the doping concentration of the three distinct device regions: XX-YY-ZZ refers to the dopant concentration order of magnitude in the source, channel, and drain regions, respectively. For example, 17-17-17 refers to a device structure with doping concentration of 10 17 cm -3 in all three regions, while 18-17-19 refers to a device configuration wherein the doping concentration is 10 18 cm -3 in the source region, 10 17 cm -3 in the channel region, and 10 19 cm -3 in the drain region. As seen in Fig. 2(b), devices employing a drain composition of In 0.25 Ga 0.75 As and a uniform doping concentrations of 10 18 cm -3 (red curve) and 10 19 cm -3 (blue curve) throughout displayed no distinguishable transistor characteristics due to minimal variations between the ON and OFF state currents. However, the transfer characteristics improved significantly for the same drain composition when using a constant doping concentration of 10 17 cm -3 (i.e., 17-17-17 case; black curve), evidenced by an I ON /I OFF 1. For all cases, the gate length is equal to the channel length, which is expresses as L g = L ch . Note that the oxide thicknesses in b and c are 10 nm and 1 nm, respectively ratio of 2.66 × 10 5 and a subthreshold slope of 62.4 mV/dec. These results indicate that while the device demonstrates improved transfer characteristics, there remains potential for enhancing the drain current through further modifications in its composition and doping level. This suggests that a more precise doping strategy, potentially involving graded or asymmetric doping profiles, could further improve charge transport and transistor efficiency.
Further investigations of the conduction band diagram for the device configuration with the 17-17-17 doping profile and x = 0.25 drain composition, shown in Fig. 2(d), reveal that the band structure in the drain region did not form an effective well shape for electron capture from the channel, suggesting a need for further optimization. In response, we conducted a comprehensive study using a fixed doping profile of 18-17-19 while the drain In x Ga 1-x As composition was varied for values of x = 0.25, 0.50, and 0.75, as depicted in Fig. 1(b). The results are shown in Fig. 2(b) indicated by the brown, purple, and green curves, respectively, with a magnified view of the 1.0 V to 1.3 V gate voltage range presented in Fig. 2(c). These configurations consistently demonstrated enhanced transfer characteristics, achieving an improved I ON /I OFF ratio of 4.33 × 10 5 and an ON state current of 7.52 × 10 -5 A/µm for the 18-17-19 doping profile with In 0.25 Ga 0.75 As drain composition. These results indicate that optimizing both doping and drain composition significantly enhances electron transport, thereby improving overall transistor performance. Figure 2(c) further illustrates how variations in doping and composition influence ON state current, providing insights into the relationship between material properties and device efficiency.
In junctionless architectures, effective gate control is crucial for establishing an efficient source-to-channel barrier height modulation [56,57]. Better control in barrier height mitigates short-channel effects by regulating electron transport from the source to the drain. Consequently, there is a substantial overlap between the valence band in the channel region and conduction band in the drain region [58]. The closely spaced energy bands in these structures support band-to-band tunneling (BTBT) from the channel to the drain region. This mechanism is akin to the lateral band-toband tunneling (L-BTBT) witnessed in the phenomenon of gate-induced drain leakage (GIDL) in nanowire-based MOS-FETs, suggesting a commonality in tunneling behaviors across different semiconductor device architectures [59][60][61]. For the In 0.5 Ga 0.5 As drain composition, an overlap has been teristics shown in b across the 1.0 to 1.3 gate voltage range. (d -f) Conduction band (red) and valance band (black) profiles for the following DG source/channel/drain device architectures: d In 0.5 Ga 0.5 As/ InAs/In 0.25 Ga 0.75 As with 17-17-17 doping profile; e In 0.5 Ga 0.5 As/ InAs/In 0.5 Ga 0.5 As with 18-17-19 doping profile; and f In 0.5 Ga 0.5 As/ InAs/In 0.25 Ga 0.75 As with 18-17-19 doping profile
observed between the conduction band and the valance band in the -0.65 eV to -0.8 eV energy range, as illustrated in Fig. 2(e). To overcome the potential BTBT effect, we tuned the drain region composition to In 0.25 Ga 0.75 As. As clearly seen in Fig. 2(f), a separation between the conduction and valance band on the drain side is observed in this case, which results in greater drain current (orange curve in Fig. 2(c)) when compared to other drain compositions. The above noted bandgap engineering and dopant concentration modulation strategies resulted in an optimized device architecture with doping profile of 18-17-19 and composition profile of In 0.5 Ga 0.5 As/InAs/In 0.25 Ga 0.75 As in source, channel, and drain, respectively. We adopt this optimized device configuration in simulations of EDL-gated transistors with fixed and bias-dependent ionic concentration in the electrolyte, which is schematically represented in Fig. 1(c). In Fig. 1(b), the device features a 10 nm HfO₂ gate dielectric, whereas in Fig. 1(c), the interfacial HfO₂ thickness is significantly reduced to just 1 nm to represent the effect of the Stern layer and account for ion size considerations. While the capacitance of the 1 nm HfO₂ layer is in series with that of the electrolyte, its impact on the total capacitance is minimal due to its extremely thin nature and high dielectric constant. Previous studies have shown that such configurations in TCAD can accurately represent the electrostatic ionic gating effect when compared to experimental results [31]. The dominant capacitance contribution still arises from the EDL at the electrolyte interface, which provides superior electrostatic control. This distinction explains why the electrolyte-gated device in Fig. 1(c) achieves better performance metrics compared to the metal-gated device in Fig. 1(b). The high capacitance of the EDL effectively compensates for the series capacitance effect introduced by the thin HfO₂ layer, ensuring enhanced gate control and improved transistor operation.
To simulate the electrolyte-gated transistor, we used a 300 nm electrolyte region and 1 nm HfO 2 layer as the interfacial oxide to capture the electrostatic behavior and properties of the electrolyte/channel interface, as well as to prevent electrolyte-to-semiconductor ion migration (Fig. 1(c)). To emulate the ionic dynamics in the electrolyte region, we considered fixed N c = N v = 10 32 cm -3 , corresponding to an experimentally accessible ion concentration known to facilitate effective gating [32,33,38,39]. Figure 3(a) shows a comparison of the transfer characteristics of the DG device structure without (black) and with (red) an electrolyte medium, where the channel thickness is 50 nm in both cases. Notably, the integration of the electrolyte results in an improved SS of 62.3 mV/dec, I ON /I OFF of 1.1 × 10 6 , and drain-induced barrier lowering (DIBL) of 21 mV. Bias-dependent net ion concentrations in the electrolyte are plotted in Fig. 3(b) across a region spanning 50 nm from electrolyte/channel interface. At the electrolyte/semiconductor interface at V g = 1.3 V, a net ion concentration of 4.5 × 10 19 cm -3 was extracted. The formation of the ionic layer at the electrolyte/semiconductor interface can be understood from the device configuration contour plot of cation concentration, shown in Fig. 3(c). The high cation density at the interface confirms that electrolytemediated gating is effectively realized, validating the capability of electrolyte gating to enhance charge modulation in the transistor.
Having demonstrated the effective operation of an electrolyte-gated device, we now analyze how gate length variations influence key figures of merit (FOM) in the dual-gated structure with a channel thickness of 50 nm. Understanding gate length dependence is critical for optimizing device performance, particularly in terms of electrostatic control, short-channel effects, and switching efficiency. Gate length-dependent transfer characteristics are shown in Fig. 4(a), which provides insight into the trade-offs between ON state performance and leakage current at different gate lengths. It can be observed that as gate length decreases, the ON state current increases from 1.2 × 10 -4 A/µm to 1.7 × 10 -4 A/µm, which is shown in the magnified view of the 1.2 V to 1.3 V gate voltage range in 4(b). Similarly, the OFF state current increases from 1.1 × 10 -10 A/µm to 4 × 10 -10 A/µm, which is shown in the magnified view of the 0 V to 0.15 V gate voltage range in Fig. 4(c). This phenomenon can be better understood by analyzing the device FOM, listed in Table 3.
Observations from Table 3 indicate that with an increase in gate length, the threshold voltage increases from 0.273 V to 0.322 V. Additionally, longer gate lengths are associated with lower SS and DIBL values, suggesting improved gate control. Also, I ON /I OFF ratio increases from 4.3 × 10 5 A/µm to 1.1 × 10 6 A/µm with increasing gate length. Despite these variations, the presence of short-channel effects is evident (i.e., DIBL = 21 mV for L g = 1000 nm) even though the devices show nearly ideal SS values, implying a reduced vulnerability to these effects in comparison with what is observed in traditional oxide-gated devices [62]. These findings highlight the effectiveness of electrolyte gating in mitigating short-channel effects while maintaining strong electrostatic control, making it a promising approach for future low-power, high-performance electronics.
To further optimize electrolyte-gated transistor performance, we investigate the effect of channel thickness (T ch ) variations on key figures of merit in a heterostructured III-V nanowire-based transistor. Understanding the influence of T ch is essential for balancing electrostatic control, I ON /I OFF switching behavior, and power efficiency in scaled device architectures. This study further investigates the impact of channel thickness (T ch ) variations on the performance of an electrolyte-gated heterostructured III-V nanowire-based transistor in DG configuration with a fixed gate length of L g = 1000 nm. Transfer characteristics for channel thickness variations are shown in Fig. 5(a). For devices with T ch = 30 nm, both the ON and OFF state currents are reduced Table 3 Figures of merit of DG electrolyte-gated devices with variable gate length Figure of merit L g = 200 nm L g = 400 nm L g = 600 nm L g = 800 nm L g = 1000 nm 4. In evaluating the performance of electrolyte-gated transistors, one critical parameter is the threshold voltage (Vth), which exhibits a dependence on the channel thickness. For a channel thickness of 30 nm, the transistor achieves the lowest Vth, recorded at 0.318 V, indicating optimized charge carrier control at reduced dimensions. As the channel thickness increases to 70 nm, there is a noticeable, albeit slight, rise in Vth to 0.321 V. This trend suggests a correlation between increased channel thickness and reduced gate efficiency, which could impact device scalability and performance. Additionally, the I ON /I OFF ratio, a pivotal efficiency indicator in transistor performance, shows a significant improvement with thinner channels. Specifically, at 30 nm, the I ON / I OFF ratio is an order of magnitude greater than that observed for a channel of 70 nm thickness. The reduced channel thickness in an electrolyte-gated structure further enhances this electrostatic control. As a result, the channel can be more effectively depleted in the OFF state, leading to a lower OFF state leakage current. With a lower leakage current and a relatively unchanged ON state current, the ON-OFF current ratio of the electrolyte-gated FET is significantly improved compared to conventional double-gate MOSFETs. This enhanced ratio at reduced thickness emphasizes the benefits of fine-tuning channel dimensions to optimize transistor ON-OFF behavior and overall device efficiency [63].
Another indispensable parameter in transistor characterization is the subthreshold slope, which serves as an indicator of gate controllability. The SS demonstrates near-ideal behavior at 30 nm, with a value of 60.7 mV/dec, suggesting excellent gate control at this scale. As the channel thickness increases, there is a gradual increase in SS, indicating a decrease in gate efficiency, which can be attributed to the extended channel dimensions impacting the electrostatic control by the gate [64].
The collective figures of merit from these observations indicate that while thinner channel electrolyte-gated transistors exhibit superior gate control, which enhances the overall device performance, thicker channels struggle with gate controllability. This diminished control is directly reflected in their higher threshold voltages, highlighting the challenges associated with scaling up channel thickness. Thinner channel MOSFETs generally perform better than thicker channel MOSFETs due to several key factors related to electrostatic control, short-channel effects, and overall device efficiency. A thinner channel enhances the gate's electrostatic influence over the entire channel region, leading to better ON/ Table 4 Figures of merit of DG electrolyte-gated devices with variable channel thickness Figure of merits T ch = 30 nm T ch = 40 nm T ch = 50 nm T ch = 60 nm T ch = 70 nm Vth (V) 0.318 0.312 0.322 0.321 0.321 I off × 10 -11 (A/µm) 2.1 5.0 11 22 46 I on × 10 -04 (A/µm) 1.0 1.1 1.2 1.3 1.4 I ON /I OFF 4.9 × 10 6 2.3 × 10 6 1.1 × 10 6 6.0 × 10 5 3.2 × 10 5 Subthreshold slope (mV/dec) 60.7 61.6 62.3 63.1 65.0
OFF switching characteristics, reduced subthreshold leakage currents, and lower threshold voltages, which in turn lowers power consumption [65]. Additionally, thinner channels mitigate short-channel effects, such as drain-induced barrier lowering and velocity saturation, resulting in better device scalability and performance in smaller geometries [66]. The improved subthreshold swing in thinner channels allows for rapid transitions from OFF to ON states, enhancing switching speed and reducing power consumption during idle states [67]. Carrier mobility also benefits from thinner channels due to reduced surface scattering and fewer impurities, leading to higher performance. These advantages make thinner channel MOSFETs more efficient and reliable, driving the overall advancement of semiconductor technology and enabling the development of faster, smaller, and more energy-efficient electronic devices. These findings provide vital insights into the design and optimization of next-generation transistors, where balancing channel dimensions with gate control is crucial for advancing semiconductor technologies. The feasibility of further miniaturization of electrolyte-gated NW transistors is supported by previous studies demonstrating that InAs NW-based transistors with diameters as small as 10 nm maintain strong electrostatic control and operational efficiency [70]. Reducing NW dimensions enhances gate coupling, allowing for improved subthreshold slope and lower power consumption. However, extreme miniaturization may introduce quantum confinement effects and increased surface scattering, which could impact carrier mobility. The results in Fig. 5 suggest that optimizing channel thickness to smaller dimensions, such as 30 nm, already provides significant performance improvements. This supports the potential for further device scaling while maintaining electrostatic integrity and enhancing transistor performance for future nanoelectronic device applications. Additionally, carrier density induced by EDL gating has shown to be independent of the electrolyte thickness and can be thinned to 10 nm or smaller [47]. Figure 5 reveals that optimizing channel thickness is essential for achieving high-performance transistors. Thinner channels, due to their enhanced gate control, can operate at lower voltages, thereby reducing power consumption and heat generation. This is particularly beneficial in the development of portable electronic devices, where battery life and thermal management are critical concerns. Moreover, the enhanced performance of electrolyte-gated transistors contributes to faster processing speeds and more efficient data handling, facilitating advancements in fields such as neuromorphic computing and edge computing [68,69].
To further refine the accuracy of electrolyte-gated transistor simulations, we now incorporate bias-dependent ionic concentrations, which more realistically model the dynamic behavior of the electrolyte interface. This approach allows us to capture variations in ion density under different applied biases, providing a more precise representation of electrostatic modulation compared to fixed ionic concentration models. In previous simulations, device structures were modeled using a fixed ionic concentration, mimicked through the use of fixed effective DOS values of N c = N v = 10 32 cm⁻ 3 . We now simulate devices with bias-dependent ionic concentrations, which are directly extracted by COMSOL simulations for different bias points [35,47]. These bias point-specific ionic concentrations are then converted into conduction and valance band effective density of states as an input for Silvaco's TCAD simulations. This methodology is highlighted as one of the unique computation aspects of the current study as it more accurately represents the changes in ion density under different applied biases. Details of the calculations are discussed in Sect. 2. We compared the transfer characteristics for device without electrolyte gating and with electrolyte gating considering both fixed and bias-dependent ionic concentrations, as shown in Fig. 6.
It is apparent from Fig. 6 that the threshold voltage is lower in the device with electrolyte gating. Lower threshold voltages, due to the formation of a high-capacitance EDL at the electrolyte-semiconductor interface, necessitates a lower applied gate voltage to achieve channel inversion. Additionally, the presence of mobile ions in the electrolyte causes higher electrostatic coupling, increases the effective gate voltage reaching the channel and further reduces the threshold voltage. While only a minor Vth reduction is observed here, the compounding impacts become significant in the case of densely integrated, multichannel device configurations.
In comparison, for a fixed effective density of states, the threshold voltage registers 0.008 V lower than in the biasdependent case. This discrepancy arises because, in the bias-dependent configuration, the effective density of states in the electrolyte, which correlate to ionic concentration, is lower at smaller bias levels. Conversely, for the fixed effective density of states, the analysis assumes the maximum value, representative of the ionic concentration at the highest bias point. This assumption significantly influences the ion dynamics and the formation of the EDL on both sides of the electrolyte layer, which, in turn, impacts the electrostatic control within the channel and results in the observed change in threshold voltage [47].
Moreover, a significant improvement in performance is noted between the devices without electrolyte and those with bias-dependent electrolyte gating. The latter shows an I ON / I OFF ratio of 5.33 × 10 6 , indicating enhanced efficiency in current modulation. Additionally, the subthreshold slope, a critical parameter indicative of how swiftly a transistor can switch from OFF to ON states, demonstrates ideal characteristics in the electrolyte-gated device with bias-dependent values of effective density states (N c and N v ), measuring at 60 mV/dec. This optimal SS suggests that the bias-dependent device maintains excellent control over channel conductivity, even at reduced channel thicknesses. Such characteristics indicate the device's strong potential for low-power logic applications, where optimizing power consumption while maintaining high performance is critical. These findings reinforce the advantages of electrolyte gating in future transistor designs, particularly in enabling energy-efficient, high-performance electronics.
In this work, the performance of electrolyte-gated, junctionless, III-V heterostructured nanowire transistors was evaluated through a comprehensive series of TCAD simulations using both fixed and bias-dependent electrolyte ionic concentrations. The nanowire device architecture consisted of axial In x Ga 1-x As source, InAs channel, and In x Ga 1-x As drain segments encapsulated by a 1 nm-thick HfO 2 layer, which served to mimic the Stern layer at the interface between the semiconductor nanowire and an enveloping electrolyte medium when an EDL is formed under an applied bias. Thus, the HfO 2 layer served to capture the electrostatics of the EDL, while preventing charge transfer between the III-V channel and the gated electrolyte, which was effectively modeled as a semiconductor. This study specifically compares the performance of two transistor configurations: one with a 1 nm HfO₂ interfacial layer acting as the Stern layer combined with an electrolyte gate and another with a 10 nm HfO₂ dielectric without electrolyte gating. This distinction is crucial, as the presence of the electrolyte enables the formation of an EDL, which enhances electrostatic control and reduces operating voltages. The results demonstrate that the 1 nm HfO₂ plus electrolyte configuration yields improved gate modulation, a lower subthreshold swing, and a higher ON/OFF ratio compared to the conventional 10 nm HfO₂-only device. This comparison underscores the critical role of electrolyte gating in achieving superior transistor performance.
The enhanced performance of electrolyte-gated transistors is primarily due to the formation of an EDL at the electrolyte/semiconductor interface, which serves as an ultra-thin, high-capacitance gate dielectric. This strong electrostatic coupling allows for improved charge carrier modulation, reduced operating voltages, and superior gate control. Compared to conventional oxide-gated transistors, the EDL mechanism results in improved subthreshold slopes, higher ON/OFF current ratios, and enhanced switching performance, making it an excellent choice for energy-efficient electronic device applications.
The optimization of electrolyte-gated junctionless III-V nanowire transistors is pivotal to advancing high-performance, low-power electronic devices for next-generation logic applications. These transistors exhibit strong electrostatic control due to their gate-all-around architecture, effectively mitigating short-channel effects and enabling efficient operation at reduced supply voltages. Such improvements are essential for developing energy-efficient electronics that demand high-speed switching and minimal power dissipation. By incorporating electrolyte gating, these devices achieve near-ideal subthreshold slopes and enhanced ON/ OFF current ratios, positioning them as promising candidates for future low-power computing technologies. First, the performance dependences of a nanowire-based MOS-FET device architecture upon the composition and dopant concentration in the source, channel, and drain regions were independently investigated. An optimized dual-gated device configuration was achieved that consisted of an In 0.5 Ga 0.5 As source region with doping concentration of 1 × 10 18 cm -3 , an InAs channel region with doping concentration of 1 × 10 17 cm -3 , and an In 0.25 Ga 0.75 As drain region with doping concentration of 1 × 10 19 cm -3 . Upon III-V composition and doping profile optimizations, an electrolyte layer was integrated, and simulations were conducted with fixed N c and N v values that captures experimentally accessible ion concentrations, resulting in a subthreshold slope of 62.3 mV/ dec and an I ON /I OFF ratio of 10 6 . For comparison, devices without electrolyte gating exhibited an SS of 63.2 mV/ dec and an I ON /I OFF ratio of 10 5 . Simulations exploring the influence of variable gate lengths at a constant thickness of 50 nm demonstrated that increasing the gate length within the 200 nm to 1000 nm range enhances the I ON /I OFF ratio while only marginally reducing both DIBL and SS, suggesting that electrolyte-gated transistors become more susceptible to short-channel effects as the axial dimension of the nanowire channel is scaled down. Moreover, channel thickness variations from 30 to 70 nm indicated that a thickness of 30 nm achieves nearly ideal SS of 60.7 mV/dec and an I ON /I OFF of 10 6 , while a thickness of 70 nm results in an SS of 65 mV/dec and an I ON /I OFF of 10 5 , confirming that thinner channel dimensions facilitate better gate control. Finally, additional simulations were performed using bias-dependent ionic concentrations applied to an EDL-gated III-V nanowire transistor for the first time. For a dual-gated device geometry with channel thickness of 30 nm and gate length of 1000 nm, superior FET performance was realized resulting in an I ON / I OFF ratio of 10 6 , an SS of 60 mV/dec, and a Vth of 0.318 V.
The novelty of this study lies in the comprehensive optimization of doping profiles and device architectures, as well as the consideration of bias-dependent ionic concentrations, which ultimately demonstrate the significant impact of electrolyte gating on key device performance metrics. The findings provide valuable insights into the design of high-performance transistors with potential applications in next-generation low-power and highefficiency electronics. Despite the benefits of electrolyte gating, this study has some limitations. The simulations consider ideal electrolyte behavior, overlooking potential long-term ion diffusion and stability issues under continuous operation. While 2D simulations effectively capture key device physics, a full 3D simulation would offer a more accurate representation of nanowire confinement effects. Additionally, the DOS calculations rely on a classical approach, whereas quantum mechanical methods could provide a more precise assessment of electronic states and carrier transport properties. Further detailed studies that include quantum mechanical analyses of device structures consisting of channel thicknesses below 30 nm and their corresponding logic performance metrics will be the focus of future investigations.