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Polynomial multiplication stands out as a highly demanding arithmetic process in the development of post-quantum cryptosystems. The importance of the number-theoretic transform (NTT) extends beyond post-quantum cryptosystems, proving valuable in enhancing existing security protocols such as digital signature schemes and hash functions. CRYSTALS-KYBER stands out as the sole public key encryption (PKE) algorithm chosen by the National Institute of Standards and Technology (NIST) in its third round selection, making it highly regarded as a leading post-quantum cryptography (PQC) solution. Faults have the potential to disrupt cryptographic systems, compromise data integrity, and enable side-channel attacks, making the incorporation of robust error detection mechanisms essential. This article introduces algorithm-level fault detection schemes in the NTT multiplication using Negative Wrapped Convolution (NWC) and the NTT tailored forKyber Round 3, representing a significant enhancement compared with previous research. We evaluate this through the simulation of a fault model, ensuring that the conducted assessments accurately mirror the obtained results. Our fault detection scheme is designed to address both malicious fault injection attacks on Kyber and naturally occurring faults. Furthermore, we assessed the effectiveness of the proposed error detection scheme for the NTT implemented in bothNWC andKyber, using AMD/Xilinx Artix-7 FPGA, HLS and processor-based approaches. In our FPGA implementation ofNWC, the integration of our error detection approach achieves near-100% fault coverage with minimal area overhead and results in only a 12% increase in latency compared with the original hardware design. Finally, we attained an error detection ratio of nearly 100% for the NTT operation inKyber, with a clock cycle overhead of 16% on the Cortex-A72 processor.
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This content will become publicly available on October 23, 2026
$$\mu $$ Scan: Deep Learning Detection of Faulty Micro-architecture States and Patterns from Scan-Chain Data
Hardware Fault injection can leave processors in weird micro-architecture states that evade detection by conventional software-level monitors, jeopardizing system reliability. We propose μScan, a deep learning framework that leverages scan-chain observability to detect such anomalous states. μScan fine-tunes a large language model (LLM) to clas-sify single-cycle processor states as weird or sane, achieving an average clas-sification accuracy of 92% and maintaining robust performance across dif-ferent CPU architectures (MSP430, PICO (RV32IC), IBEX (RV32IMC)). We further refine this LLM classifier with reinforcement learning, which sharpens its decision boundaries and improves detection of borderline anomalies. μScan also employs a graph neural network (GNN) to ana-lyze multi-cycle fault patterns, capturing complex temporal dependencies that single-cycle analysis might miss. This GNN-based analysis success-fully identifies recurring fault sequences and maps them to known Common Weakness Enumeration (CWE) vulnerability classes, revealing potential hardware design flaws. μScan demonstrates scalability and generalization on multiple processor architectures (including micro-coded and pipelined cores) and is evaluated with both pre-silicon simulation data and a post-silicon prototype. Our results show that μScan enables early detection of micro-architecture vulnerabilities in the design phase and provides a robust post-silicon anomaly detection mechanism.
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- Award ID(s):
- 2219810
- PAR ID:
- 10681566
- Publisher / Repository:
- Springer Nature Switzerland
- Date Published:
- ISBN:
- 978-3-032-01799-4
- Page Range / eLocation ID:
- 124 to 143
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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