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Hardware security creates a hardware-based security foundation for secure and reliable operation of systems and applications used in our modern life. The presence of design for security, security assurance, and general security design life cycle practices in product life cycle of many large semiconductor design and manufacturing companies these days indicates that the importance of hardware security has been very well observed in industry. However, the high cost, time, and effort for building security into designs and assuring their security - due to using many manual processes - is still an important obstacle for economy of secure product development. This paper presents several promising directions for automation of design for security and security assurance practices to reduce the overall time and cost of secure product development. First, we present security verification challenges of SoCs, possible vulnerabilities that could be introduced inadvertently by tools mapping a design model in one level of abstraction to its lower level, and our solution to the problem by automatically mapping security properties from one level to its lower level incorporating techniques for extension and expansion of the properties. Then, we discuss the foundation necessary for further automation of formal security analysis of a design by incorporating threat model and common security vulnerabilities into an intermediate representation of a hardware model to be used to automatically determine if there is a chance for direct or indirect flow of information to compromise confidentiality or integrity of security assets. Finally, we discuss a pre-silicon-based framework for practical and time-and-cost effective power-side channel leakage analysis, root-causing the side-channel leakage by using the automatically generated leakage profile of circuit nodes, providing insight to mitigate the side-channel leakage by addressing the high leakage nodes, and assuring the effectiveness of the mitigation by reprofiling the leakage to prove its acceptable level of elimination. We hope that sharing these efforts and ideas with the security research community can accelerate the evolution of security-aware CAD tools targeted to design for security and security assurance to enrich the ecosystem to have tools from multiple vendors with more capabilities and higher performance.
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This content will become publicly available on August 24, 2026
Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System-on-Chip Design
While traditional side-channel leakage assessment relies on physical measurements from fabricated hardware, pre-silicon leakage assessment – conducted through simulation – faces the challenge of estimating real-world leakage before hardware is available. Current pre-silicon methods seek to improve simulation accuracy by increasing the design detail at a single level of abstraction. However, there is always a limit to the level of detail that can be incorporated, leaving a gap between simulation and physical measurements. We show that side-channel leakage analysis can be approached as a top-down problem, using a hierarchical assessment across multiple abstraction levels in a design, enabling to gradually uncover sources of side-channel leakage. We introduce Telescope, a topdown framework for pre-silicon side-channel leakage assessment across three abstraction levels: architecture-, micro-architecture-, and gate-level. Telescope’s primary contribution is to demonstrate the propagation of leakage from software instructions to hardware implementation, revealing that leakage does not manifest uniformly across design levels. Through this cross-level analysis, we identify the origins of leakage at each abstraction level and explore their interdependencies. This analysis uncovers three distinct leakage patterns across levels: progressive, emergent, and disappearing sidechannel leakage. We demonstrate the scalability of Telescope by applying it to two RISC-V processors: the multi-cycle PicoRV32 and the pipelined IBEX. We analyze their power-based side-channel leakage patterns across several benchmarks, and illustrate practical use cases in debugging of side-channel leakage issues, and verification of micro-architecture effects in side-channel leakage.
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- Award ID(s):
- 2219810
- PAR ID:
- 10681567
- Publisher / Repository:
- ACM
- Date Published:
- ISBN:
- 9798400714108
- Page Range / eLocation ID:
- 1280 to 1293
- Format(s):
- Medium: X
- Location:
- Hanoi Vietnam
- Sponsoring Org:
- National Science Foundation
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