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The classical paging problem, introduced by Sleator and Tarjan in 1985, formalizes the problem of caching pages in RAM in order to minimize IOs. Their online formulation ignores the cost of address translation: programs refer to data via virtual addresses, and these must be translated into physical locations in RAM. Although the cost of an individual address translation is much smaller than that of an IO, every memory access involves an address translation, whereas IOs can be infrequent. In practice, one can spend money to avoid paging by over-provisioning RAM; in contrast, address translation is effectively unavoidable. Thus address-translation costs can sometimes dominate paging costs, and systems must simultane- ously optimize both. To mitigate the cost of address translation, all modern CPUs have translation lookaside buffers (TLBs), which are hardware caches of common address translations. What makes TLBs interesting is that a single TLB entry can potentially encode the address translation for many addresses. This is typically achieved via the use of huge pages, which translate runs of contiguous virtual addresses to runs of contiguous physical addresses. Huge pages reduce TLB misses at the cost of increasing the IOs needed to maintain contiguity in RAM. This tradeoff between TLB misses and IOs suggests that the classical paging problem does not tell the full story. This paper introduces the Address-Translation Problem, which formalizes the problem of maintaining a TLB, a page table, and RAM in order to minimize the total cost of both TLB misses and IOs. We present an algorithm that achieves the benefits of huge pages for TLB misses without the downsides of huge pages for IOs.
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This content will become publicly available on May 1, 2027
FRACTAL: Fast Reverse Address translation over Coherence for Tracing And Logging
Fine-grained tracing of memory activity is useful for analyzing software behavior and understanding software-hardware interactions. Existing approaches rely either on software instrumentation, which introduces high overhead, or on architecture-specific hardware tracing mechanisms with limited flexibility and filtering capabilities. In particular, current solutions provide limited support for process-specific filtering and/or simultaneous visibility of virtual and physical addresses. This paper presents FRACTAL, a hardware module that operates in the coherence domain and enables tracing of memory transactions for a target process. FRACTAL passively observes coherence traffic and performs reverse address translation to reconstruct virtual addresses from physical memory accesses. To achieve this, it follows the page table walks of the monitored process and maintains a reverse translation structure that mirrors the processor TLB. The design is largely microarchitecture-agnostic, does not require binary instrumentation, and does not affect the performance of the traced application. We implement FRACTAL on a commercial heterogeneous multiprocessor system-on-chip platform, the KRIA KV260, with programmable logic integrated in the cache-coherent interconnect. Experimental evaluation using vision benchmarks shows that the system can do fine-grained tracing of selected virtual address ranges with negligible overhead. The results demonstrate that coherence-based observation combined with reverse translation is a practical approach for low-intrusion memory tracing.
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- Award ID(s):
- 2238476
- PAR ID:
- 10684885
- Publisher / Repository:
- In Proceedings of the 5th Real-time And intelliGent Edge computing workshop at Cyber-Physical Systems and Internet of Things Week 2026
- Date Published:
- Format(s):
- Medium: X
- Location:
- Saint Malo, France
- Sponsoring Org:
- National Science Foundation
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