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This paper presents a comprehensive analysis of the impact of intra-pair PN skew compensation in printed circuit board (PCB) strip line (SL) traces, for a high-speed 224 Gbps lane for the first time. The study investigates the effects of skew compensation placement both with and without via discontinuities. Detailed evaluations are performed in both time and frequency domains, examining critical parameters such as time-domain reflectometry (TDR), input impedance, return loss, insertion loss, and common-mode S -parameters. The findings reveal that, in a simple strip line trace without via discontinuities, the location of skew compensation has negligible influence on signal margins. However, when via discontinuities are introduced, the impact becomes significant on signal margins and common-mode conversion. This highlights the crucial role of skew compensation placement in high-speed designs, where increasingly tight performance margins and reduced PCB dimensions exacerbate signal integrity challenges. The results underscore the importance of careful design considerations to optimize performance in modern high-speed interconnects.
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This content will become publicly available on August 18, 2026
Multi-Objective Inverse Optimization of High-Speed Interconnects Using Cascaded Deep Neural Network
This paper proposes a novel multi-objective inverse optimization method for high-speed interconnects based on a cascaded deep neural network (DNN) structure, which can efficiently optimize characteristic impedance, insertion loss, and far-end crosstalk (FEXT) simultaneously. Parameter optimization for high-speed interconnects is essential to the signal integrity and electrical performance of complex designs such as multilayer printed circuit boards (PCBs) and chiplets. Conventional optimization approaches often rely on numerous optimization iterations, which is highly time-consuming, especially in highdimensional parameter spaces. This paper proposes a novel DNNbased method by cascading an inverse-prediction network and a forward-prediction network to achieve multi-objective optimization for characteristic impedance, insertion loss, and FEXT by optimizing the trace width, trace spacing, and pair-topair distance. Further, by incorporating an integer programming technique, parameter optimization of multilayer PCBs, including the PCB stackup and design parameters of each signal layer, can be accomplished in seconds, much more efficiently than the conventional optimization approaches.
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- Award ID(s):
- 1916535
- PAR ID:
- 10696605
- Publisher / Repository:
- IEEE
- Date Published:
- ISBN:
- 979-8-3315-0874-6
- Page Range / eLocation ID:
- 120 to 125
- Subject(s) / Keyword(s):
- Stripline Printed circuits Integrated circuit interconnections Optimization methods Artificial neural networks Insertion loss Machine learning Nonhomogeneous media Impedance Optimization Neural Network Deep Neural Network Multi-objective Optimization Inverse Optimization High-speed Interconnects Optimization Method Design Parameters Integration Of Signals Printed Circuit Board Insertion Loss Electrical Performance Conventional Optimization Multi-objective Optimization Method Deep Neural Network Structure High-dimensional Parameter Space Root Mean Square Error Input Parameters Hidden Layer Inverse Problem NSGA-II Arrangement Of Layers Multi-objective Optimization Algorithm Pareto Front Dielectric Thickness Impedance Values Forward Model Optimization Variables Deep neural network high-speed interconnects machine learning multi-objective optimization PCB stack-up
- Format(s):
- Medium: X
- Location:
- Raleigh, NC, USA
- Sponsoring Org:
- National Science Foundation
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