%AYadavali, Sagar%ALee, Daeyeon%AIssadore, David%BJournal Name: Scientific Reports; Journal Volume: 9; Journal Issue: 1; Related Information: CHORUS Timestamp: 2022-12-17 07:56:10 %D2019%INature Publishing Group %JJournal Name: Scientific Reports; Journal Volume: 9; Journal Issue: 1; Related Information: CHORUS Timestamp: 2022-12-17 07:56:10 %K %MOSTI ID: 10153652 %PMedium: X %TRobust Microfabrication of Highly Parallelized Three-Dimensional Microfluidics on Silicon %X
We present a new, robust three dimensional microfabrication method for highly parallel microfluidics, to improve the throughput of on-chip material synthesis by allowing parallel and simultaneous operation of many replicate devices on a single chip. Recently, parallelized microfluidic chips fabricated in Silicon and glass have been developed to increase the throughput of microfluidic materials synthesis to an industrially relevant scale. These parallelized microfluidic chips require large arrays (>10,000) of Through Silicon Vias (TSVs) to deliver fluid from delivery channels to the parallelized devices. Ideally, these TSVs should have a small footprint to allow a high density of features to be packed into a single chip, have channels on both sides of the wafer, and at the same time minimize debris generation and wafer warping to enable permanent bonding of the device to glass. Because of these requirements and challenges, previous approaches cannot be easily applied to produce three dimensional microfluidic chips with a large array of TSVs. To address these issues, in this paper we report a fabrication strategy for the robust fabrication of three-dimensional Silicon microfluidic chips consisting of a dense array of TSVs, designed specifically for highly parallelized microfluidics. In particular, we have developed a two-layer TSV design that allows small diameter vias (