%ASridharan, Amitesh%AAngizi, Shaahin%ACherupally, Sai%AZhang, Fan%ASeo, Jae-Sun%AFan, Deliang%D2022%I %K %MOSTI ID: 10389143 %PMedium: X %TA 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm %XWe present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V. Country unknown/Code not availablehttps://doi.org/10.1109/ESSCIRC55480.2022.9911440OSTI-MSA