<?xml version="1.0" encoding="UTF-8"?><rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:dcq="http://purl.org/dc/terms/"><records count="1" morepages="false" start="1" end="1"><record rownumber="1"><dc:product_type>Conference Paper</dc:product_type><dc:title>Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5</dc:title><dc:creator>Andrzejczak, Michal; Farahmand, Farnoud; Gaj, Kris</dc:creator><dc:corporate_author/><dc:editor/><dc:description>We describe a generic high-speed hardware architecture for the lattice-based post-quantum cryptosystem Round5. This architecture supports both public-key encryption (PKE) and a key encapsulation mechanism (KEM). Due to several hardware-friendly features, Round5 can achieve very high performance when implemented in modern FPGAs.</dc:description><dc:publisher/><dc:date>2019-12-01</dc:date><dc:nsf_par_id>10174999</dc:nsf_par_id><dc:journal_name>2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico</dc:journal_name><dc:journal_volume/><dc:journal_issue/><dc:page_range_or_elocation>1 to 2</dc:page_range_or_elocation><dc:issn/><dc:isbn/><dc:doi>https://doi.org/10.1109/ReConFig48160.2019.8994765</dc:doi><dcq:identifierAwardId>1801512</dcq:identifierAwardId><dc:subject/><dc:version_number/><dc:location/><dc:rights/><dc:institution/><dc:sponsoring_org>National Science Foundation</dc:sponsoring_org></record></records></rdf:RDF>