Journal ArticleTAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignGuo, Licheng; Chi, Yuze; Lau, Jason; Song, Linghao; Tian, Xingyu; Khatti, Moazin; Qiao, Weikang; Wang, Jie; Ustun, Ecenur; Fang, Zhenman; Zhang, Zhiru; Cong, Jason<p>In this article, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of convenient APIs that allows users to easily express flexible and complex inter-task communication structures. Second, TAPA adopts a coarse-grained floorplanning step during HLS compilation for accurate pipelining of potential critical paths. In addition, TAPA implements several optimization techniques specifically tailored for modern HBM-based FPGAs. In our experiments with a total of 43 designs, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. Notably, in 16 experiments, we make the originally unroutable designs achieve 274 MHz, on average. The framework is available at<ext-link ext-link-type='url' href='https://github.com/UCLA-VAST/tapa'>https://github.com/UCLA-VAST/tapa</ext-link>and the core floorplan module is available at<ext-link ext-link-type='url' href='https://github.com/UCLA-VAST/AutoBridge'>https://github.com/UCLA-VAST/AutoBridge</ext-link></p>ACM Transactions on Reconfigurable Technology and Systems2023-12-3110550474ACM Transactions on Reconfigurable Technology and Systems1641 to 311936-7406https://doi.org/10.1145/36093351937599National Science Foundation