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The biocompatibility of materials used in electronic devices is critical for the development of implantable devices like pacemakers and neuroprosthetics, as well as in future biomanufacturing. Biocompatibility refers to the ability of these materials to interact with living cells and tissues without causing an adverse response. Therefore, it is essential to evaluate the biocompatibility of metals and semiconductor materials used in electronic devices to ensure their safe use in medical applications. Here, we evaluated the biocompatibility of a collection of diced silicon chips coated with a variety of metal thin films, interfacing them with different cell types, including murine mastocytoma cells in suspension culture, adherent NIH 3T3 fibroblasts, and human induced pluripotent stem cell (iPSC)-derived neural progenitor cells (NPCs). All materials tested were biocompatible and showed the potential to support neural differentiation of iPSC-NPCs, creating an opportunity to use these materials in a scalable production of a range of biohybrid devices such as electronic devices to study neural behaviors and neuropathies. 

Hafnium-oxide based bipolar RRAM was investigated for high-level temporal correlation detection, for in-memory computing. The experimental analog data of HfO2 RRAM, both in RESET and SET regimes was evaluated to detect 10 correlated processes from 25 processes on a 5x5 RRAM array. Our method gave 36,000-53,000 times less energy consumption than that of a previous implementation with phase change memory, and a predicted acceleration of 1600-2100 times the execution time than that of 1xPOWER8 CPU (1 thread) for detecting correlation between 25 processes. 

RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The non-ideal output from the RRAM macro, due to device and circuit non-idealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. On the algorithm side, we develop a framework for the training of DNNs to support the hybrid IMC architecture through ensemble learning. The proposed framework performs quantization (weights and activations), pruning, RRAM IMC-aware training, and employs ensemble learning through different compensation scales by utilizing the programmable shifter. Finally, we design a silicon prototype of the proposed hybrid IMC architecture in the 65nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows that the SRAM compensation allows for a realistic IMC architecture with multi-level RRAM cells (MLC) even though they suffer from high variations. The hybrid IMC architecture achieves up to 21.9%, 12.65%, and 6.52% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead, for ResNet-20 on CIFAR-10, VGG-16 on CIFAR-10, and ResNet-18 on ImageNet, respectively.