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As large-scale data processing becomes increasingly essential in today’s world, balancing developer productivity and computational performance in high-performance computing (HPC) environments remains a persistent challenge. Conventional HPC workloads rely heavily on MPI-based solutions, often written in C for the better performance. Meanwhile, Apache Arrow, specifically leveraging Arrow Flight for node-to-node data transfers, has gained traction as a flexible, in-memory columnar data approach that promises efficient, language-agnostic memory usage, although its usage in HPC environments is less exploredIn this paper, we perform a preliminary study that consists of three different implementations of the same data-parallel workload — the "Monte Carlo Simulation for Financial Risk Assessment" — in (1) MPI in C, (2) MPI in Python, and (3) Python-based Arrow. Specifically, we measure and compare the trade-offs between performance and lines of code for each implementation. In addition, we demonstrate the scalability of each implementation through a strong-scaling analysis, highlighting potential communication bottlenecks as we add more communicators. The results of this paper are intended to surface early trends for balancing developer productivity, raw performance, and scalability when selecting tools for large-scale computational tasks. 

The unpredictability of real-world graph workloads complicates the realization of high-performance graph analytics on the GPU. For example, variance in sparsity and neighbor commonality can dramatically alter computing costs and memory-access patterns, even within different regions of the same graph.In this paper, we investigate Jaccard similarity, a metric that measures the similarity of two sets. We compare and contrast the performance an edge-centric parallelization of Jaccard similarity with respect to the vertex-centric approach from NVIDIA’s cuGraph library. We then characterize the impact of graph metrics (e.g., average degree, maximum degree, Gini index) on the performance of edge-centric and vertex-centric kernels. By combining the above graph metrics with performance metrics (e.g., bandwidth utilization and thread activity), we deliver insight into why certain graphs benefit from edge-centric over vertex-centric parallelization, while other graphs benefit conversely. Finally, based on these results, we make a case for sparsity-aware parallelization, i.e., choosing between an edge-centric or a vertex-centric parallelized kernel, for improved performance by showing that selecting the best-performing parallelized kernel can deliver a geometric mean speedup of 3.2× over the reference cuGraph kernel on an NVIDIA A100 GPU. 

Mission-critical edge applications often demand FFTs under the stringent constraints of performance, accuracy, and power. With many vendor FFT libraries only supporting power-of-two FFTs, the need for zero-padding of non-power-of-two inputs to facilitate the use of power-of-two FFT libraries can degrade accuracy by introducing spectral artifacts and increase power consumption by unnecessarily computing on zeroes. Furthermore, striking the right balance between performance, accuracy, and power can significantly impact developer productivity and, in turn, delay deployment.To address the limitations imposed by these constraints, we realize a mixed-radix FFT (MR-FFT) for 1,600-and 8,000-point inputs on a low-power FPGA that uses a high-level synthesis approach to enable efficient design exploration. Specifically, our MR-FFT on a krtkl Snickerdoodle board, which features an ARM Cortex-A9 CPU and Xilinx Artix-7 FPGA, (1) maintains or improves accuracy when compared to power-of-two FFT with zero-padding, (2) achieves 2.5× lower power consumption and 1.3× better energy efficiency over a Raspberry Pi CM5 GPU, and (3) delivers an average of 4.9× speedup over the NumPy FFT implementation on the Cortex-A9 CPU. 

As FPGAs and GPUs continue to make inroads into high-performance computing (HPC), the need for languages and frameworks that offer performance, productivity, and portability across heterogeneous platforms, such as FPGAs and GPUs, continues to grow. OpenCL and SYCL have emerged as frameworks that offer cross-platform functional portability between FPGAs and GPUs. While functional portability across a diverse set of platforms is an important feature of portable frameworks, achieving performance portability often requires vendor and platform-specific optimizations. Achieving performance portability, therefore, comes at the expense of productivity. This paper presents a quantification of the tradeoffs between performance, portability, and productivity of OpenCL and SYCL. It extends and complements our prior work on quantifying performance-productivity tradeoffs between Verilog and OpenCL for the FPGA. In addition to evaluating the performance-productivity tradeoffs between OpenCL and SYCL, this work quantifies the performance portability (PP) of OpenCL and SYCL as well as their code convergence (CC), i.e., a measure of productivity across different platforms (e.g., FPGA and GPU). Using two applications as case studies (i.e., edge detection using the Sobel filter, and graph link prediction using the Jaccard similarity index), we characterize the tradeoffs between performance, portability, and productivity. Our results show that OpenCL and SYCL offer complementary tradeoffs. While OpenCL delivers better performance portability than SYCL, SYCL offers better code convergence and a 1.6× improvement in source lines of code over OpenCL. 

Stochastic block partitioning (SBP) is a community detection algorithm that is highly accurate even on graphs with a complex community structure, but its inherently serial nature hinders its widespread adoption by the wider scientific community. To make it practical to analyze large real-world graphs with SBP, there is a growing need to parallelize and distribute the algorithm. The current state-of-the-art distributed SBP algorithm is a divide-and-conquer approach that limits communication between compute nodes until the end of inference. This leads to the breaking of computational dependencies, which causes convergence issues as the number of compute nodes increases and when the graph is sufficiently sparse. To address this shortcoming, we introduce EDiSt — an exact distributed stochastic block partitioning algorithm. Under EDiSt, compute nodes periodically share community assignments during inference. Due to this additional communication, EDiSt improves upon the divide-and-conquer algorithm by allowing it to scale out to a larger number of compute nodes without suffering from convergence issues, even on sparse graphs. We show that EDiSt provides speedups of up to 26.9x over the divide-and-conquer approach and speedups up to 44.0x over shared memory parallel SBP when scaled out to 64 compute nodes. 

Community detection, or graph partitioning, is a fundamental problem in graph analytics with applications in a wide range of domains including bioinformatics, social media analysis, and anomaly detection. Stochastic block partitioning (SBP) is a community detection algorithm based on sequential Bayesian inference. SBP is highly accurate even on graphs with a complex community structure. However, it does not scale well to large real-world graphs that can contain upwards of a million vertices due to its sequential nature. Approximate methods that break computational dependencies improve the scalability of SBP via parallelization and data reduction. However, these relaxations can lead to low accuracy on graphs with complex community structure. In this paper, we introduce additional synchronization steps through vertex-level data batching to improve the accuracy of such methods. We then leverage batching to develop a high-performance parallel approach that improves the scalability of SBP while maintaining accuracy. Our approach is the first to integrate data reduction, shared-memory parallelization, and distributed computation, thus efficiently utilizing distributed computing resources to accelerate SBP. On a one-million vertex graph processed on 64 compute nodes with 128 cores each, our approach delivers a speedup of 322x over the sequential baseline and 6.8x over the distributed-only implementation. To the best of our knowledge, this Graph Challenge submission is the highest-performing SBP implementation to date and the first to process the one-million vertex graph using SBP. 

Deep reinforcement learning has found use cases in many applications, such as natural language processing, self-driving cars, and spacecraft control applications. Many use cases of deep reinforcement learning methodologies impose additional restrictions on the underlying hardware that runs policy evaluation algorithms. For example, in many mission-critical systems, the deployment of reinforcement learning often requires inference with low latency and high accuracy. Recent studies in machine learning have explored the impact of pruning the trained network and shown that pruning the network can improve the accuracy and performance of the inference. Inspired by the recent studies on the effects of pruning trained networks, this work explores the efficacy of the network pruning technique via the AMD Vitis AI toolchain for reinforcement learning models. In particular, we evaluate the soft actor-critic (SAC) model that is trained to solve the MuJoCo humanoid environment, where the objective of the humanoid agent is to learn a policy that allows it to stay in motion for as long as possible without falling over. During the training phase, we prune the model using the weight sparsity pruner from the Vitis AI optimizer at different timesteps. Our experiments show that pruning leads to an improvement in the reinforcement learning policy evaluation, where the trained agent can remain mobile in the environment and accumulate higher rewards compared to a trained agent without pruning. Specifically, we observe that pruning the network during training can deliver up to 23% higher reward and 20% better mean episode length compared to a network without any pruning.