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  1. Abstract

    Recent studies have demonstrated the importance of temporal regulation of pathogen defense by the circadian clock. However, our understanding of the molecular basis underlying this role of the circadian clock is still in its infancy. We report here the mechanism by which the Arabidopsis master clock protein CCA1 regulates an output target gene GRP7 for its circadian expression and function in pathogen defense. Our data firmly establish that CCA1 physically associates with the GRP7 promoter via the predicted CCA1-binding motif, evening element (EE). A site-directed mutagenesis study showed that while individual EE motifs differentially contribute to robust circadian expression of GRP7, abolishing all four EE motifs in the proximal GRP7 promoter disrupts rhythmicity of GRP7 expression and results in misalignment of defense signaling mediated by GRP7 and altered pathogen responses. This study provides a mechanistic link of the circadian regulation of an output gene to its biological function in pathogen defense, underscoring the importance of temporal control of plant innate immunity.

  2. Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS) , accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework— AutoDSE —that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9× speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38× while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towardsmore »democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.« less
    Free, publicly-accessible full text available July 31, 2023
  3. Free, publicly-accessible full text available June 13, 2023