Search for: All records

Scientific applications generate an unprecedented volume of data, overwhelming the network and file systems’ bandwidth and posing challenges for efficient and scalable data retrieval and analysis. Progressive data compression offers a promising solution by enabling on-demand retrieval at reduced size. However, existing progressive methods either fail to bound the errors in essential quantities of interest (QoIs) derived from raw data or suffer from suboptimal retrieval efficiency. In this work, we propose QProR, an efficient QoI-based progressive framework that optimizes progressive retrieval for target QoIs. Our key contributions include: (1) a systematic framework that integrates error-controlled lossy compressors with bitplane encoding while decoupling the two processes for high flexibility and adaptability; (2) a novel weighted bitplane encoding method which incorperates QoI knowledge into data refactoring to enhance retrieval efficiency; (3) an optimized retrieval strategy that accounts for the varying impacts of different variables on multivariate QoIs; (4) comprehensive evaluations using six real-world datasets from multiple scientific applications and thorough comparisons against state of the arts. Experimental results demonstrate that QProR achieves up to reduction in the retrieval size under the same requested QoI error tolerance, when compared with the best-performing existing methods. When transferring 384 GB of scientific data to remote sites, QProR delivers up to 1.68 × speedup in the end-to-end data transfer performance. 

While Graph Neural Networks excel at graph learning, they are limited by the 1-Weisfeiler-Leman (WL) test and sensitive to structural changes. Recent work addressed the 1-WL test limitation by introducing Graph Transformers (GTs), which combine a Transformer encoder layer with a graph convolution layer. This allows nodes to attend to long-range dependencies without structural inductive bias. However, the self-attention mechanism in GTs primarily focuses on node features and local substructures, neglecting the crucial high-order connectivity patterns, i.e., topological features, in reasoning the underlying graph structure. Our proposed Topology-Induced Graph Transformer (TOPGT) addresses this gap. TOPGT leverages both graph convolution and Transformer layers to learn the loca topological features of the graph, enhancing the expressiveness of the 1-WL test concerning these features. Experiments on graph classification tasks on various benchmark datasets show that TOPGT achieves highly competitive results on all datasets and demonstrates the significant advantages of leveraging the topological information of the graph data in feature space and the powerful learning ability based on the transformer architecture. 

Not AvailableAs applications demand more bandwidth, the “memory wall” problem becomes increasingly severe. Therefore, the processing-in-memory (PIM) architecture has attracted significant research interest due to its ability to execute instructions offloaded by the processor. Existing works on PIM architectures are classified into two categories: regional offloading, where all instructions within a programmer-specified code region are offloaded, and selective offloading, where only instructions of interest are offloaded via hardware support. However, PIM architectures pose the amplified in-PIM traffic overhead challenge that endangers the performance of PIM and degrades the performance of the entire system. To address the challenge, we propose a PIM architecture, called fast PIM (fPIM), which integrates the PIM cache within each Channel Controller to optimize the data flow within the PIM. This design cooperates with the Processing Unit Load-balancer and Behavior-based Offloader to achieve high execution efficiency. To evaluate fPIM, we perform extensive experiments, and the results show that fPIM reduces the workload finish time by up to 88.6%, 87.5%, and 79.6% (with an average of 68.7%, 66.2%, and 59.8%), compared to three state-of-the-art PIM designs, PEI, Fafnir, and SpaceA, respectively. 

With the increasing problem complexity, more irregular applications are deployed on high-performance clusters due to the parallel working paradigm, and yield irregular memory access behaviors across nodes. However, the irregularity of memory access behaviors is not comprehensively studied, which results in low utilization of the integrated hybrid memory system compositing of stacked DRAM and off-chip DRAM. To address this problem, we devise a novel method called Similarity-Managed Hybrid Memory System (SM-HMS) to improve the hybrid memory system performance by leveraging the memory access similarity among nodes in a cluster. Within SM-HMS, two techniques are proposed, Memory Access Similarity Measuring and Similarity-based Memory Access Behavior Sharing. To quantify the memory access similarity, memory access behaviors of each node are vectorized, and the distance between two vectors is used as the memory access similarity. The calculated memory access similarity is used to share memory access behaviors precisely across nodes. With the shared memory access behaviors, SM-HMS divides the stacked DRAM into two sections, the sliding window section and the outlier section. The shared memory access behaviors guide the replacement of the sliding window section while the outlier section is managed in the LRU manner. Our evaluation results with a set of irregular applications on various clusters consisting of up to 256 nodes have shown that SM-HMS outperforms the state-of-the-art approaches, Cameo, Chameleon, and Hyrbid2, on job finish time reduction by up to 58:6%, 56:7%, and 31:3%, with 46:1%, 41:6%, and 19:3% on average, respectively. SM-HMS can also achieve up to 98:6% (91:9% on average) of the ideal hybrid memory system performance.