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  1. Free, publicly-accessible full text available September 1, 2024
  2. The Brillouin instability (BI) caused by stimulated Brillouin scattering (SBS) can limit the output power of high-energy laser amplifiers. Pseudo-random bitstream (PRBS) phase modulation is an effective modulation technique to suppress BI. In this paper, we study the impact of the PRBS order and modulation frequency on the BI threshold for different Brillouin linewidths. PRBS phase modulation with a higher order will break the power into a larger number of frequency tones with a lower maximum power in each tone, leading to a higher BI threshold and a smaller tone spacing. However, the BI threshold may saturate when the tone spacing in the power spectra approaches the Brillouin linewidth. For a given Brillouin linewidth, our results allow us to determine the order of PRBS beyond which there is no further improvement in the threshold. When a specific threshold power is desired, the minimum PRBS order required decreases as the Brillouin linewidth increases. When the PRBS order is too large, the BI threshold deteriorates, and this deterioration occurs at smaller PRBS orders as the Brillouin linewidth increases. We investigate the dependence of the optimal PRBS order on the averaging time and fiber length, and we did not find a significant dependence. We also derive a simple equation that relates the BI threshold for different PRBS orders. Hence, the increase in BI threshold using an arbitrary order PRBS phase modulation may be predicted using the BI threshold from a lower PRBS order, which is computationally less time-consuming to compute.

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  3. The continuous growth of CNN complexity not only intensifies the need for hardware acceleration but also presents a huge challenge. That is, the solution space for CNN hardware design and dataflow mapping becomes enormously large besides the fact that it is discrete and lacks a well behaved structure. Most previous works either are stochastic metaheuristics, such as genetic algorithm, which are typically very slow for solving large problems, or rely on expensive sampling, e.g., Gumbel Softmax-based differentiable optimization and Bayesian optimization. We propose an analytical model for evaluating power and performance of CNN hardware design and dataflow solutions. Based on this model, we introduce a co-optimization method consisting of nonlinear programming and parallel local search. A key innovation in this model is its matrix form, which enables the use of deep learning toolkit for highly efficient computations of power/performance values and gradients in the optimization. In handling power-performance tradeoff, our method can lead to better solutions than minimizing a weighted sum of power and latency. The average relative error of our model compared with Timeloop is as small as 1%. Compared to state-of-the-art methods, our approach achieves solutions with up to 1.7 × shorter inference latency, 37.5% less power consumption, and 3 × less area on ResNet 18. Moreover, it provides a 6.2 × speedup of optimization 
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  4. Observation of intrinsic quantum transport properties of two-dimensional (2D) topological semimetals can be challenging due to suppression of high mobility caused by extrinsic factors introduced during fabrication. We demonstrate current annealing as a method to substantially improve electronic transport properties of 2D topological semimetal flakes. Contact resistance and resistivity were improved by factors up to [Formula: see text] and [Formula: see text], respectively, in devices based on exfoliated flakes of two topological semimetals, ZrSiSe and BaMnSb 2 . Using this method, carrier mobility in ZrSiSe was improved by a factor of 3800, resulting in observation of record-high mobility for exfoliated ZrSiSe. Quantum oscillations in annealed ZrSiSe appeared at magnetic fields as low as 5 T, and magnetoresistance increased by a factor of 10 4 . We argue that a thermal process underlies this improvement. Finally, Raman spectroscopy and analysis of quantum oscillations in ZrSiSe indicate that the phonon modes and Fermi surface area are unchanged by current annealing. 
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  5. The Brillouin instability (BI) due to stimulated Brillouin scattering (SBS) and the transverse (thermal) mode instability (TMI) due to stimulated thermal Rayleigh scattering (STRS) limit the achievable power in high-power lasers and amplifiers. The pump power threshold for BI increases as the core diameter increases, but the threshold for TMI may decrease as the core diameter increases. In this paper, we use a multi-time-scale approach to simultaneously model BI and TMI, which gives us the ability to find the fiber diameter with the highest power threshold. We formulate the equations to compare the thresholds of the combined and individual TMI and BI models. At the pump power threshold and below, there is a negligible difference between the full and individual models, as BI and TMI are not strong enough to interact with each other. The highest pump threshold occurs at the optimal core size of 43µm for the simple double-clad geometry that we considered. We found that both effects contribute equally to the threshold, and the full BI and TMI model yields a similar threshold as the BI or TMI model alone. However, once the reflectivity is sufficiently large, we find in the full BI and TMI model that BI may trigger TMI and reduce the TMI threshold to a value lower than is predicted in simulations with TMI alone. This result cannot be predicted by models that consider BI and TMI separately. Our approach can be extended to more complex geometries and used for their optimization.

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  6. Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO’s), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement. 
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