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Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by conventional von Neumann computers. A key requirement for p-computing is the realization of fast, compact, and energy-efficient probabilistic bits. Stochastic magnetic tunnel junctions (MTJs) with low energy barriers, where the relative dwell time in each state is controlled by current, have been proposed as a candidate to implement p-bits. This approach presents challenges due to the need for precise control of a small energy barrier across large numbers of MTJs, and due to the need for an analog control signal. Here we demonstrate an alternative p-bit design based on perpendicular MTJs that uses the voltage-controlled magnetic anisotropy (VCMA) effect to create the random state of a p-bit on demand. The MTJs are stable (i.e. have large energy barriers) in the absence of voltage, and VCMA-induced dynamics are used to generate random numbers in less than 10 ns/bit. We then show a compact method of implementing p-bits by using VC-MTJs without a bias current. As a demonstration of the feasibility of the proposed p-bits and high quality of the generated random numbers, we solve up to 40 bit integer factorization problems using experimental bit-streams generated by VC-MTJs. Our proposal can impact the development of p-computers, both by supporting a fully spintronic implementation of a p-bit, and alternatively, by enabling true random number generation at low cost for ultralow-power and compact p-computers implemented in complementary metal-oxide semiconductor chips.

 

Due to their interesting physical properties, myriad operational regimes, small size, and industrial fabrication maturity, magnetic tunnel junctions are uniquely suited for unlocking novel computing schemes for in-hardware neuromorphic computing. In this paper, we focus on the stochastic response of magnetic tunnel junctions, illustrating three different ways in which the probabilistic response of a device can be used to achieve useful neuromorphic computing power. 

Abstract Magnetic random-access memory (MRAM) based on voltage-controlled magnetic anisotropy in magnetic tunnel junctions (MTJs) is a promising candidate for high-performance computing applications, due to its lower power consumption, higher bit density, and the ability to reduce the access transistor size when compared to conventional current-controlled spin-transfer torque MRAM. The key to realizing these advantages is to have a low MTJ switching voltage. Here, we report a perpendicular MTJ structure with a high voltage-controlled magnetic anisotropy coefficient ~130 fJ/Vm and high tunnel magnetoresistance exceeding 150%. Owing to the high voltage-controlled magnetic anisotropy coefficient, we demonstrate sub-nanosecond precessional switching of nanoscale MTJs with diameters of 50 and 70 nm, using a voltage lower than 1 V. We also show scaling of this switching mechanism down to 30 nm MTJs, with voltages close to 2 V. The results pave the path for the future development and application of voltage-controlled MRAMs and spintronic devices in emerging computing systems. 

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.