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We prove the conjectured classification of topological phases in two spatial dimensions with gappable boundary, in a simplified setting. Two gapped ground states of lattice Hamiltonians are in the same quantum phase of matter, or topological phase, if they can be connected by a constant-depth quantum circuit. It is conjectured that the Levin-Wen string-net models exhaust all possible gapped phases with gappable boundary, and these phases are labeled by unitary modular tensor categories. We prove this under the assumption that every phase has a representative state with zero correlation length satisfying the entanglement bootstrap axioms, or a strict form of area law. Our main technical development is to transform these states into string-net states using constant-depth quantum circuits. 

Growing interconnect bandwidth demand in large datacenters requires energy-efficient optical transceivers that operate with four-level pulse amplitude modulation (PAM4) to enable high per-wavelength data rates. Further increases in bandwidth density is possible by leveraging wavelength-division multiplexing (WDM), which optical link architectures based on silicon photonic microring modulators (MRMs) and drop filters inherently enable. This paper presents high-speed PAM4 transmitter and receiver front-ends implemented in a 28nm CMOS process that are co-designed with these silicon photonic optical devices to enable energy-efficient operation. The transmitter utilizes an optical digital-to-analog converter (DAC) approach with two PAM2 AC-coupled pulsed-cascode high-swing voltage-mode output stages to drive the MRM MSB/LSB segments. A 3.42Vppd output swing is achieved when operating at 80Gb/s PAM4 with an energy efficiency of 3.66pJ/bit. The receiver front-end interfaces with a silicon-germanium avalanche photodiode (APD) and utilizes a low-bandwidth input transimpedance amplifier followed by continuous-time linear equalizer and variable-gain amplifier stages. Biasing the APD to realize a gain of 2 allows for -7dBm optical modulation amplitude (OMA) sensitivity at 56Gb/s PAM4 with a BER=10-4 and an energy efficiency of 1.61pJ/bit. Experimental verification of the full PAM4 transceiver at 50Gb/s operation shows -4.66dBm OMA sensitivity at a BER~4x10-4. 

We perform a detailed resource estimate for the prospect of using deep entanglement renormalization ansatz (DMERA) on a fault-tolerant quantum computer, focusing on the regime in which the target system is large. For probing a relatively large system size (64×64), we observe up to an order of magnitude reduction in the number of qubits, compared to the approaches based on quantum phase estimation (QPE). We discuss two complementary strategies to measure the energy. The first approach is based on a random sampling of the local terms of the Hamiltonian, requiring (1/ϵ2) invocations of quantum circuits, each of which have depth of at most (logN), where ϵ is the relative precision in the energy and N is the system size. The second approach is based on a coherent estimation of the expectation value of observables averaged over space, which achieves the Heisenberg scaling while incurring only a logarithmic cost in the system size. For estimating the energy per site of ϵ, (logNϵ) T gates and (logN) qubits suffice. The constant factor of the leading contribution is shown to be determined by the depth of the DMERA circuit, the gates used in the ansatz, and the periodicity of the circuit. We also derive tight bounds on the variance of the energy gradient, assuming the gates are random Pauli rotations. 

We propose a fault-tolerant quantum error correction architecture consisting of a linear array of emitters and delay lines. In our scheme, a resource state for fault-tolerant quantum computation is generated by letting the emitters interact with a stream of photons and their neighboring emitters. Depending on the number of emitters ne, we study the effect of delay line errors in two regimes: when ne is a small constant of order unity and when ne scales with the code distance. Between these two regimes, the logical error rate steadily decreases as ne increases, from a scaling of exp(−cη−1/2) to exp(−c′η−1), where η is the error rate per unit length in the delay line, for some constants c,c′>0. We also carry out a detailed study of the break-even point and the fault-tolerance overhead. These studies suggest that the multi-emitter architecture, using the state-of-the-art delay lines, can be used to demonstrate error suppression, assuming other sources of errors are sufficiently small. 

Digital content services provide users with a wide range of content, such as news, articles, or movies, while monetizing their content through various business models and promotional methods. Unfortunately, poorly designed or unpro- tected business logic can be circumvented by malicious users, which is known as business flow tampering. Such flaws can severely harm the businesses of digital content service providers. In this paper, we propose an automated approach that discov- ers business flow tampering flaws. Our technique automatically runs a web service to cover different business flows (e.g., a news website with vs. without a subscription paywall) to collect execution traces. We perform differential analysis on the execution traces to identify divergence points that determine how the business flow begins to differ, and then we test to see if the divergence points can be tampered with. We assess our approach against 352 real-world digital content service providers and discover 315 flaws from 204 websites, including TIME, Fortune, and Forbes. Our evaluation result shows that our technique successfully identifies these flaws with low false-positive and false- negative rates of 0.49% and 1.44%, respectively.