Search for: All records

This study reports a binder-free, catalyst-free method for fabricating vertically aligned carbon nanotubes (VACNTs) directly on copper (Cu) foil using plasma-enhanced chemical vapor deposition (PECVD) for electrochemical double-layer capacitor (EDLC) applications. This approach eliminates the need for catalyst layers, polymeric binders, or substrate pre-treatments, simplifying electrode design and enhancing electrical integration. The resulting VACNTs form a dense, uniform, and porous array with strong adhesion to the Cu substrate, minimizing contact resistance and improving conductivity. Electrochemical analysis shows gravimetric specific capacitance (Cgrav) and areal specific capacitance (Careal) of 8 F g−1 and 3.5 mF cm−2 at a scan rate of 5 mV/s, with low equivalent series resistance (3.70 Ω) and charge transfer resistance (0.48 Ω), enabling efficient electron transport and rapid ion diffusion. The electrode demonstrates excellent rate capability and retains 92% of its initial specific capacitance after 3000 charge–discharge cycles, indicating strong cycling stability. These results demonstrate the potential of directly grown VACNT-based electrodes for high-performance EDLCs, particularly in applications requiring rapid charge–discharge cycles and sustained energy delivery. 

VACNTs decorated with SnO₂nanoparticles exhibit enhanced charge storage through synergistic EDLC and pseudocapacitance, delivering high gravimetric specific capacitance, energy, and power densities for supercapacitor applications. 

High-power electronics, such as GaN high electron mobility transistors (HEMTs), are expected to perform reliably in high-temperature conditions. This study aims to gain an understanding of the microscopic origin of both material and device vulnerabilities to high temperatures by real-time monitoring of the onset of structural degradation under varying temperature conditions. This is achieved by operating GaN HEMT devices in situ inside a transmission electron microscope (TEM). Electron-transparent specimens are prepared from a bulk device and heated up to 800 °C. High-resolution TEM (HRTEM), scanning TEM (STEM), energy-dispersive x-ray spectroscopy (EDS), and geometric phase analysis (GPA) are performed to evaluate crystal quality, material diffusion, and strain propagation in the sample before and after heating. Gate contact area reduction is visible from 470 °C accompanied by Ni/Au intermixing near the gate/AlGaN interface. Elevated temperatures induce significant out-of-plane lattice expansion at the SiNx/GaN/AlGaN interface, as revealed by geometry-phase GPA strain maps, while in-plane strains remain relatively consistent. Exposure to temperatures exceeding 500 °C leads to almost two orders of magnitude increase in leakage current in bulk devices in this study, which complements the results from our TEM experiment. The findings of this study offer real-time visual insights into identifying the initial location of degradation and highlight the impact of temperature on the bulk device’s structure, electrical properties, and material degradation. 

Abstract Resistive switching (RS) devices with ultra‐low‐voltage threshold and reliable switching repeatability exhibits great potential applications in energy‐efficient data storage and neuromorphic computing. Understanding switching mechanisms at nanoscale is critical to design RS devices with improved performance. In this work, a lamella memristive device using focused ion beam (FIB) method based on the metal/TiO_x/TiN/Si structure device is fabricated. In situ transmission electron microscopy (TEM) and current–voltage (I–V) characteristic demonstrate that the lamella device shows a volatile RS behavior with a threshold switching at ≈ ± 0.4 V. In situ scanning transmission electron microscopy (STEM) experiments with electron energy loss spectroscopy (EELS) reveal that the charge carriers such as oxygen vacancies migrate under positive/negative DC bias and modulate Schottky barriers at the top and bottom metal/semiconductor interfaces. The RS mechanism of the lamella device is based on the Schottky barriers modulation and Joule heating assisted electric field triggered thermal runaway (FTTR) occurred at the metal/semiconductor interfaces. The fundamental insights gained from this study presents a perspective on interface‐type RS devices processing and opens up new technological opportunities of fabricating ultra‐low‐energy memristive devices.