We present our third and final generation joint P and S global adjoint tomography (GLAD) model, GLAD-M35, and quantify its uncertainty based on a low-rank approximation of the inverse Hessian. Starting from our second-generation model, GLAD-M25, we added 680 new earthquakes to the database for a total of 2160 events. New P-wave categories are included to compensate for the imbalance between P- and S-wave measurements, and we enhanced the window selection algorithm to include more major-arc phases, providing better constraints on the structure of the deep mantle and more than doubling the number of measurement windows to 40 million. Two stages of a Broyden–Fletcher–Goldfarb–Shanno (BFGS) quasi-Newton inversion were performed, each comprising five iterations. With this BFGS update history, we determine the model’s standard deviation and resolution length through randomized singular value decomposition.
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MGARD: A multigrid framework for high-performance, error-controlled data compression and refactoringFree, publicly-accessible full text available December 1, 2024
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Die-stacked DRAM (a.k.a., on-chip DRAM) provides much higher bandwidth and lower latency than off-chip DRAM. It is a promising technology to break the “memory wall”. Die-stacked DRAM can be used either as a cache (i.e., DRAM cache) or as a part of memory (PoM). A DRAM cache design would suffer from more page faults than a PoM design as the DRAM cache cannot contribute towards capacity of main memory. At the same time, obtaining high performance requires PoM systems to swap requested data to the die-stacked DRAM. Existing PoM designs fall into two categories - line-based and page-based. The former ensures low off-chip bandwidth utilization but suffers from a low hit ratio of on-chip memory due to limited temporal locality. In contrast, page-based designs achieve a high hit ratio of on-chip memory albeit at the cost of moving large amounts of data between on-chip and off-chip memories, leading to increased off-chip bandwidth utilization and significant system performance degradation. To achieve a similar high hit ratio of on-chip memory as pagebased designs, and eliminate excessive off-chip traffic involved, we propose SELF, a high performance and bandwidth efficient approach. The key idea is to SElectively swap Lines in a requested page that are likely to be accessed according to page Footprint, instead of blindly swapping an entire page. In doing so, SELF allows incoming requests to be serviced from the on-chip memory as much as possible, while avoiding swapping unused lines to reduce memory bandwidth consumption. We evaluate a memory system which consists of 4GB on-chip DRAM and 12GB offchip DRAM. Compared to a baseline system that has the same total capacity of 16GB off-chip DRAM, SELF improves the performance in terms of instructions per cycle by 26.9%, and reduces the energy consumption per memory access by 47.9% on average. In contrast, state-of-the-art line-based and page-based PoM designs can only improve the performance by 9.5% and 9.9%, respectively, against the same baseline system.more » « less